參數(shù)資料
型號： MT90866AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA344
封裝： 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344
文件頁數(shù)： 37/86頁
文件大?。?/td> 701K
代理商： MT90866AG2
MT90866
Data Sheet
37
Zarlink Semiconductor Inc.
Figure 15 - Block Diagram of the PLL Module
18.1 Skew Control
The circuit delays a selected reference input with a tapped delay line with seven taps - see Figure 16, "Skew
Control Circuit Diagram" on page 37. The maximum delay of the per unit delay element is factored at intervals of
3.5ns. The tap is selected by the SKEW_CONTROL bus which is programmed by the SKC2-SKC0 bits of the DPLL
Output Adjustment (DPOA) register. The skew of this input will result in a static phase offset which varies from 0 to
7 steps of the maximum delay per unit delay element, between the input and the outputs of the DPLL.
Figure 16 - Skew Control Circuit Diagram
18.2 Maximum Time Interval Error (MTIE)
The MTIE circuit prevents any significant change in the output clock phase during a reference switch. Because the
input references can have any relationship between their phases and the output follows the selected input
reference, any switch from one reference to another could cause a large phase jump in the output clock if such a
circuit did not exist. This large phase jump could cause significant data loss. The MTIE circuit keeps the phase
difference between the output clock of the DPLL and the input reference the same as if the reference switch had not
taken place.
The MTIE circuit has two modes:
Measuring mode - the circuit measures the phase difference between the new reference from the Skew
Control circuit and the feedback signal (FEEDBACK) from the Frequency Select MUX circuit. This mode is
active during the movement of the DPLL from the Holdover to the Normal Mode, and is set by the
MTIE_START signal of the State machine module. The measured value is stored into a counter and used in
the Delay mode. When the measurement process is done, the State Machine module is notified by
generating the MTIE_DONE signal, allowing it to go to the Normal Mode.
Loop
Filter
DCO
Divider
Phase
Detector
PHASE_OFFSET
Phase
Offset
FREQ_MOD
HOLDOVER
Adder
Frequency
Select
C64
CT_C8
C2M
CT_FRAME
C1M5o
FEEDBACK
Phase
Slope
Limiter
MUX
HOLDOVER_RESET
Skew
Control
(Fig 18)
REF
MTIE
FRAME
SKEW_CONTROL
M
M
MTIE_RESET
REF_VIR
M
reference
input
SKEW_CONTROL
delayed
reference
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