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參數(shù)資料
| 型號(hào)： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 21/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
21
Zarlink Semiconductor Inc.
7.0 Local Output Timing Considerations
The output data of the MT90866’s local side is slightly advanced with respect to the frame and bit boundary as
defined by the local output clocks and frame pulses (ST_FPo0, ST_CKo0, ST_FPo1, ST_CKo1). The advancement
is in the range of 5ns to 17ns. Despite this advancement, the MT90866 will operate within the parameters specified
in the datasheet because input data are usually sampled at the 3/4 or 1/2 point of the bit cell. However, the user
should be cautious when introducing additional delay to the clock signals only (e.g., by passing them through glue
logic, FPGA, or CPLD), which will introduce a few nanoseconds of delay relative to the data. If the clock signal is
delayed, data will be advanced from the receiver device’s point of view. This may cause errors in sampling the data.
Using an example where a 3/4 sampling point is used, there is about 30 ns from the sampling point to the end of the
bit cell. With a worst-case of 17ns advancement, the timing margin will be approximately 13 ns. Any additional
delays applied to the local output clocks (ST_CKo0 and ST_CKo1) must not exceed 13 ns minus the hold time of
the receiving device. Delays applied to both clocks and data equally will not impact the device operation.
8.0 Memory Block Programming
The MT90866 block programming mode (BPM) register provides users with the capability of initializing the local
and backplane connection memories in two frames. The local connection memory is partitioned into high and low
parts. Bit 13 - bit 15 of every backplane connection memory location will be programmed with the pattern stored in
bit 6 - bit 8 of the BPM register. Bit 13 - bit 15 of every local connection memory low location will be programmed
with the pattern stored in bits 3 to 5 of the BPM register. The other bit positions of the backplane connection
memory, the local low connection memory and all bits of the local high connection memory are loaded with zeros.
See Figure 5, "Block Programming Data in the Connection Memories" on page 22 for the connection memory
contents when the device is in block programming mode.
The block programming mode is enabled by setting the memory block program (MBP) bit of the Control register to
high. After the block programming enable (BPE) bit of the BPM register is set to high, the block programming data
will be loaded into bits 13 to 15 of every backplane connection memory location and bits 13 to 15 of every local
connection memory low location. The other connection memory bits are loaded with zeros. When the memory block
programming is completed, the device resets the BPE bit to low. See Table 11 on page 48 for the bit assignment of
the BPM register.
9.0 Delay Through the MT90866
The switching of information from the input serial streams to the output serial streams results in a throughput delay.
The device can be programmed to perform time slot interchange functions with different throughput delay
capabilities on a per-channel basis. For voice applications it is recommended to select variable throughput delay to
ensure minimum delay between input and output data. In wideband data applications it is recommended to select
constant throughput delay to maintain the frame integrity of the information through the switch.
The delay through the device varies according to the type of throughput delay selected in the BTM2 - BTM0 bits of
the backplane connection memory or LTM0 - LTM2 bits of the local connection memory as described in Table 25 on
page 63 and Table 29 on page 65, respectively.
9.1 Variable Delay Mode
The delay in this mode is dependent only on the combination of source and destination channels and is
independent of input and output streams. The minimum delays achievable in the MT90866 device are 3-channel
delay, 5-channel delay, and 10-channel delay for the 2 MB/s, 4 MB/s, and 8 MB/s respectively. The maximum delay
is one frame plus three channels, one frame plus five channels, and one frame plus ten channels for the 2 Mb/s,
4 Mb/s and 8 Mb/s modes respectively.
For the backplane interface, the variable delay mode can be programmed through the backplane connection
memory bits, BTM2 - BTM0. When BTM2 - BTM0 are programmed to “000”, it is a per-channel variable delay from
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| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
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| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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