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參數資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數： | 58/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
58
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 12
Unused
Reserved.
11
HRST
DPLL Hold Memory Reset Bit:
When HRST is low, the DPLL hold memory
circuit is in functional mode. When HRST is high, the hold memory circuit will be
reset. While the DPLL is in Holdover Mode, pulsing HRST high (or holding it high
continuously) will force the DPLL to the Freerun Mode.
10
MRST
MTIE Reset Bit:
When MRST is low, the DPLL MTIE circuit is in functional mode.
When MRST is high, the MTIE circuit will be reset - the DPLL outputs will align
with the nearest edge of the selected reference. When the MT90866 is operating
in the slave mode, this bit
MUST
be set high to reset the MTIE circuit.
9 - 8
FDM1 -
FDM0
Failure Detect Mode Bits:
These two bits control how to choose the Failure
Detection.
7
BFEN
B Clocks Fail Output Enable Bit:
When BFEN is low, FAIL_B output is disabled,
i.e., tri-stated. When BFEN is high, FAIL_B output is enabled.
6
AFEN
A Clocks Fail Output Enable Bit:
When AFEN is low, FAIL_A output is disabled,
i.e., tri-stated. When AFEN is high, FAIL_A output is enabled.
5
CNIN
CTREF1 andCTREF2 Inputs Inverted:
When CNIN is high, the CTREF1 and
CTREF2 inputs will be inverted, prior to entering the DPLL module. When CNIN is
low, the CTREF1 and CTREF2 inputs will not be inverted.
Table 21 - DPLL Operation Mode (DOM2) Register Bits
Read/Write Address: 002C
H
for DOM2 Register
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
HRST
MRST
FDM1
FDM0
BFEN
AFEN
CNIN
DIV1
DIV0
CNS2
CNS1
CNS0
FDM1
FDM0
Failure Detection Mode
0
0
Autodetect - Automatic Failure Detection by internal refer-
ence monitor circuit
0
1
External - Failure Detection
controlled by external inputs
(PRI_LOS and SEC_LOS)
1
0
Forced Primary - The DPLL is forced to use primary refer-
ence
1
1
Forced Secondary - The DPLL is forced to use secondary
reference
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相關代理商/技術參數 |
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| MT90866AL | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:WAN Access Switch |
| MT90868AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90868AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 32KX8K/8KX8K/1K X 1K 1.8V/3.3V 466BGA - Trays |
| MT90869 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 16K Digital Switch (F16kDX) |
| MT90869AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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