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參數(shù)資料
| 型號： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 24/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
24
Zarlink Semiconductor Inc.
If A13 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 8 on page 25.
The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register
(BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after
system power up to establish the desired switching configuration as explained in the Frame Alignment Timing and
Switching Configurations sections. The Control register is used to select Data or Connection Memory for microport
operations, ST-BUS output frame and clock modes, and to set Memory Block Programing and Bit Error Rate
Testing.
The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits
(MS2-0). The memory block programming bit allows users to program the entire connection memory in two frames
(see Memory Block Programming section). The memory select bits control the selection of the connection
memories or the data memories. See Table 9 on page 46 for content of the Control register.
The DMS register consists of the backplane and the local mode selection bits (BMS, LG41 - LG40, LG32 - LG30,
LG22 - LG20, LG12 - LG10 and LG02 - LG00) that are used to enable various switching modes for the backplane
and the local interfaces respectively. See Table 10 on page 47 for the content of the DMS register.
The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming
enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local
connection memories in two frames (see Memory Block Programming section). If the ODE pin is low, the backplane
CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin is high, all the
backplane CT-Bus and local ST-BUS output drivers are controlled on a per channel basis by backplane and local
connection memories, respectively. By programming BTM2 through BTM0 bits to “110” in the backplane connection
memory, the user can control the per-channel input on the backplane interface. For the local interface, users can
program LTM2 -0 bits to “110” in the local connection memory to control the per-channel high impedance output on
the local ST-BUS. See Table 11 on page 48 for the content of the BPM register.
002C
H
002D
H
002E
H
DPLL Operation Mode Register 2, DOM2
DPLL Output Adjustment Register, DPOA
DPLL House Keeping Register, DHKR
A13 - A0
Location
Table 7 - Address Map For Internal Registers (A13 = 0) (continued)
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