參數(shù)資料
型號: MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 1/76頁
文件大?。?/td> 1316K
代理商: MT90869AG
1
Zarlink Semiconductor Inc.
Features
16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 64
stream inputs and 64 stream outputs.
8,192-channel x 8,192-channel non-blocking
Backplane to Local stream switch.
8,192-channel x 8,192-channel non-blocking
Local to Backplane stream switch.
8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch.
8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch.
Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams.
Backplane port accepts 32 ST-BUS streams
with data rates of 2.048Mb/s, 4.096Mb/s,
8.192Mb/s or 16.384Mb/s in any combination,
or a fixed allocation of 16 streams at
32.768Mb/s.
Local port accepts 32 ST-BUS streams with
data rates of 2.048Mb/s, 4.096Mb/s, 8.192Mb/s
or 16.384Mb/s, in any combination.
Per-stream channel and bit delay for Local input
streams.
Per-stream channel and bit delay for Backplane
input streams.
Per-stream advancement for Local output
streams.
Per-stream advancement for Backplane output
streams.
Constant throughput delay for frame integrity.
Per-channel high impedance output control for
Local and Backplane streams.
Per-channel driven-high output control for local
and backplane streams.
High impedance-control outputs for external
drivers on backplane and local port.
December 2002
Ordering Information
MT90869AG
272 Ball - PBGA
-40 to +85
o
C
MT90869
Flexible 16K Digital Switch (F16kDX)
Data Sheet
Figure 1 - MT90869 Functional Block Diagram
Backplane Data Memories
(8,192 channels)
DS CS R/W A14-A0 DTA D15-D0
Test Port
Microprocessor Interface
and Internal Registers
V
SS (GND)
V
DD_CORE
TDi TDo TCK TRST
TMS
LSTo0-31
(8,192 locations)
RESET
Local
Interface
Connection Memory
BSTi0-31
Backplane
Timing Unit
FP8i
PLL
LSTi0-31
Interface
Backplane
BSTo0-31
Local
C8i
V
DD_IO
LCST0-3
ODE
BCST0-3
C8o
C16o
FP8o
FP16o
V
DD_PLL
Local
Timing
Unit
(8,192 locations)
Connection Memory
Backplane
Interface
Local
Local Data Memories
(8,192 channels)
BORS
LORS
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