MT90869
Data Sheet
36
Zarlink Semiconductor Inc.
10.0
Memory Built-In-Self-Test (BIST) Mode
As operation of the memory BIST will corrupt existing data, this test must only be instigated when the device is
placed “out-of-service” or isolated from live traffic.
The memory BIST mode is enabled through the microprocessor port (Section 13.14, Memory BIST Register).
Internal BIST memory controllers generate the memory test pattern (S-march) and control the memory test. The
memory test result is monitored through the Memory BIST Register when controlled via the microprocessor
interface.
11.0
JTAG Port
The MT90869 JTAG interface conforms to the Boundary-Scan IEEE 1149.1 standard. The operation of the
boundary-scan circuit shall be controlled by an external Test Access Port (TAP) Controller. JTAG is intended to be
used during the development cycle. The JTAG interface is operational when the MT90869 core (V
DD
-core) is
powered at typical voltage levels.
11.1
Test Access Port (TAP)
The Test Access Port (TAP) consists of four input pins and one output pin described as follows:
Test Clock Input (TCK)
TCK
provides the clock for the TAP Controller and is independent of any on-chip clock.
TCK
permits the
shifting of test data into or out of the Boundary-Scan register cells under the control of the TAP Controller in
Boundary-Scan Mode.
Test Mode Select Input (TMS)
The TAP controller uses the logic signals applied to the TMS input to control test operations. The TMS
signals are sampled at the rising edge of the TCK pulse. This pin in internally pulled to V
DD_IO
when not
driven from an external source.
Test Data Input (TDi)
Depending on the previously applied data to the
TMS
input, the serial input data applied to the
TDi
port is
connected either to the Instruction Register or to a Test Data Register. Both registers are described in a
Section 11.2, TAP Registers. The applied input data is sampled at the rising edge of TCK pulses. This pin is
internally pulled to V
DD_IO
when not driven from an external source.
Test Data Output (TDo)
Depending on the previously applied sequence to the
TMS
input, the contents of either the instruction
register or data register are serially shifted out towards the
TDo
. The data out of the
TDo
is clocked on the
falling edge of the
TCK
pulses. When no data is shifted through the boundary scan cells, the
TDo
output is
set to a high impedance state.
Test Reset (TRST)
TRST provides an asynchronous Reset to the JTAG scan structure. This pin is internally pulled to V
DD_IO
when not driven from an external source.
11.2
TAP Registers
The MT90869 uses the public instructions defined in the IEEE 1149.1 standard with the provision of an Instruction
Register and three Test Data Registers.
11.2.1
Test Instruction Register
The JTAG interface contains a four-bit instruction register. Instructions are serially loaded into the Instruction
Register from the
TDi
pin when the TAP Controller is in the shift-IR state. Instructions are subsequently decoded to
achieve two basic functions: to select the Test Data Register to operate while the instruction is current, and to define
the serial Test Data Register path to shift data between
TDi
and
TDo
during data register scanning.