參數(shù)資料
型號(hào): MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 61/76頁
文件大?。?/td> 1316K
代理商: MT90869AG
Data Sheet
MT90869
61
Zarlink Semiconductor Inc.
13.15
Revision Control Register
Address 3FFFh
The revision control register stores the binary value of the silicon revision number. This register is read only. The
RCR
register is configured as follows:
Table 50 - Revision Control Register (RCR) Bits
8
BISTSDL
0
Local Data Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
7
BISTCDL
0
Local Data Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
6
BISTPDL
0
Local Data Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
5
BISTSCB
0
Backplane Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
4
BISTCCB
0
Backplane Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
3
BISTPCB
0
Backplane Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
2
BISTSCL
0
Local Connection Memory Start BIST sequence.
Sequence enabled on LOW to HIGH transition.
1
BISTCCL
0
Local Connection Memory BIST sequence completed. (Read only).
High indicates completion of Memory BIST sequence.
0
BISTPCL
0
Local Connection Memory Pass/Fail Bit (Read only).
This bit indicates the Pass/Fail status following completion of the Memory BIST
sequence. A HIGH indicates Pass, a LOW indicates Fail.
Bit
Name
Reset Value
Description
15-4
Reserved
0
Reserved.
3-0
RC(3:0)
defined by silicon
Revision Control Bits.
Bit
Name
Reset
Description
Table 49 - Memory BIST Register (MBISTR) Bits (continued)
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