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參數(shù)資料
| 型號： | MT90869AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 16K Digital Switch (F16kDX) |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272 |
| 文件頁數(shù)： | 16/76頁 |
| 文件大?。?/td> | 1316K |
| 代理商： | MT90869AG |
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MT90869
Data Sheet
16
Zarlink Semiconductor Inc.
3.0
Input and Output Offset Programming
3.1
Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero such
that Ch0 is the first channel that appears after the frame boundary.
By programming the Backplane or Local input channel delay registers, BCDR0-31 and LCDR0-31, users can assign
the Ch0 position to be located at any one of the channel boundaries in a frame. For delays within channel
boundaries, the input bit delay programming can be used.
Figure 9 - Backplane and Local Input Channel Delay Timing Diagram
The use of Input Channel Delay in combination with Input Bit Delay enables the Ch0 position to be placed anywhere
within a frame to a resolution of 1/4 of the bit period.
3.2
Input Bit Delay Programming (Backplane and Local Input Streams)
In addition to the Input Channel Delay programming, the Input Bit Delay programming feature provides users with
greater flexibility when designing switch matrices for high speed operation. The input bit delay may be programmed
on a per-stream basis to accommodate delays created on PCM highways. For all streams the delay is up to 7 3/4
bits with a resolution of 1/4 bit, for the selected data-rate.
See Figure 10 and Figure 11 for Input Bit Delay Timing at 16Mb/s and 8Mb/s data rates, respectively.
The local input delay is defined by the Local Input Delay registers, LIDR0 to LIDR31, corresponding to the local data
streams, LSTi0 to LSTi31, and the backplane input delay is defined by the Backplane Input Delay registers, BIDR0
to BIDR31, which correspond to the backplane data streams, BSTi0 to BSTi31.
FP8o
C8o
7
2
3
4
5
6
1 0
BSTi0-31/LSTi0-31
Channel Delay = 0
Ch 0
7
2
3
4
5
6
1 0
Ch 1
2
3
1 0
7
2
3
4
5
6
1 0
Ch127
2
3
4
5
6
1 0
Ch126
7 6
7
2
3
4
5
6
1 0
BSTi0-31/LSTi0-31
Channel Delay = 1
Ch127
7
2
3
4
5
6
1 0
Ch 0
2
3
1 0
7
2
3
4
5
6
1 0
Ch126
2
3
4
5
6
1 0
Ch125
7 6
7
2
3
4
5
6
1 0
BSTi0-31LSTi0-31
Channel Delay = 2
Ch126
7
2
3
4
5
6
1 0
Ch127
2
3
1 0
7
2
3
4
5
6
1 0
Ch125
2
3
4
5
6
1 0
Ch0
7 6
(Default)
Channel Delay,1
Channel Delay, 2
7
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| MT90869AG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 8K X 8K DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
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| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
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