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參數(shù)資料
| 型號： | MT90869AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 16K Digital Switch (F16kDX) |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA272 |
| 封裝： | 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272 |
| 文件頁數(shù)： | 45/76頁 |
| 文件大?。?/td> | 1316K |
| 代理商： | MT90869AG |
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Data Sheet
MT90869
45
Zarlink Semiconductor Inc.
13.2
Block Programming Register (BPR)
Address 0001h.
The block programming register stores the bit patterns to be loaded into the connection memories when the
Memory Block Programming feature is enabled. The BPE, LBPD2-0 and BBPD2-0 bits in the BPR register must
be defined in the same write operation.
The BPE bit is set HIGH, to commence the block programming operation. Programming is completed in one frame
period and may be instigated at any time within a frame.The BPE bit returns to LOW to indicate the block
programming function has completed.
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except to
abort the programming operation. The programming operation may be aborted by setting either BPE to LOW, or
the Control Register bit, MBP, to LOW.
The
BPR
register is configured as follows.
.
Table 17 - Block Programming Register Bits
Bit
Name
Reset
Description
15-7
Unused
0
Set LOW.
6-4
BBPD(2:0)
0
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW
3-1
LBPD(2:0)
0
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW
0
BPE
0
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125us, upon completion of programming.
Set LOW to abort the programming operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90869AG2 | 制造商:Microsemi Corporation 功能描述:PB FREE 8K X 8K DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA |
| MT90870 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 12 k Digital Switch (F12kDX) |
| MT90870AG | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90870AG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays |
| MT90871 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX) |
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