參數(shù)資料
型號： MT90869AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 16K Digital Switch (F16kDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝： 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù)： 32/76頁
文件大?。?/td> 1316K
代理商： MT90869AG
MT90869
Data Sheet
32
Zarlink Semiconductor Inc.
6.3
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization of the Local and Backplane Connection Memories after power
up. When the Memory Block Programming mode is enabled, the contents of the Block Programming Register (BPR)
will be loaded into the connection memories. See Table 16 and Table 17 for details of the Control Register and Block
Programming Register values, respectively.
6.3.1
Memory Block Programming Procedure
Set the
MBP
bit in the Control Register from LOW to HIGH.
Set the
BPE
bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0
, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively. of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 6.
Table 6 - Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits,
BBPD2-0
, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are loaded
with zeros as shown in Table 7.
Table 7 - Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125us, to indicate completion of
memory programming.
The Block Programming Mode can be terminated at any time prior to completion by setting the
BPE
bit of the Block
Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of
LBPD2-0
and
BBPD2-0
of the Block Programming Register, following a device
reset, may be used. These settings shall set all output channels to High, or High-Impedance, in accordance with the
LORS
and
BORS
pin conditions, see Pin Description for further details. The Local Connection Memory shall be
configured to select data from Channel 0 of Backplane input Stream 0 (
BSTi0
), and the Backplane Connection
Memory shall be configured to select data from Channel 0 of Local input Stream 0 (
LSTi0
). Alternative conditions
may be established by programming bits
LBPD2-0
and
BBPD2-0
of the Block Programming Register at the time of
setting Bit
BPE
to HIGH. See Section 12.3, Local Connection Memory Bit Definition, Section 12.4, Backplane
Connection Memory Bit Definition, and Section 13.2, Block Programming Register (BPR).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
相關(guān)PDF資料
PDF描述
MT90870 Flexible 12 k Digital Switch (F12kDX)
MT90871AV Flexible 8K Digital Switch (F8KDX)
MT90871 Flexible 8K Digital Switch (F8KDX)
MT90883 TDM to Packet Processors
MT91600 Programmable SLIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90869AG2 制造商:Microsemi Corporation 功能描述:PB FREE 8K X 8K DIGITAL SWITCH 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 16KX16K/8KX8K 1.8V/3.3V 272BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F16KDX 272PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F16KDX 272PBGA
MT90870 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 12 k Digital Switch (F12kDX)
MT90870AG 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
MT90870AG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 12K X 12K/8K X 4K 1.8V/3.3V 272BGA - Trays
MT90871 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Flexible 8K Digital Switch (F8KDX)
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*