參數(shù)資料
型號(hào): MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 48/76頁
文件大?。?/td> 1316K
代理商: MT90869AG
MT90869
Data Sheet
48
Zarlink Semiconductor Inc.
13.4.1
Local Channel Delay Bits 7-0 (LCD7 - LCD0)
These eight bits define the delay, in channel numbers, the serial interface receiver take to store the channel data
from the Local stream input pins. The input channel delay can be selected to 255 (16Mb/s streams), 127 (8Mb/s
streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary.
13.5
Local Input Bit Delay Registers (LIDR0 to LIDR31)
Address 0023h to 0042h.
Thirty-two local input delay registers (LIDR0 to LIDR31) allow users to program the input bit delay for the local input
data streams LSTi0-31. The possible adjustment is up to 7 3/4 of the data rate, advancing forward with a resolution
of 1/4 of the data rate. The data rate can be either 2Mb/s, 4Mb/s, 8Mb/s or 16Mb/s.
The
LIDR0 to LIDR31
registers are configured as follows:
Table 21 - Local Channel Delay Register (LIDRn) Bits
Input Stream
Channel Delay
Corresponding
Delay Bits
LCD7-LCD0
0 Channel (Default)
0000 0000
1 Channel
0000 0001
2 Channels
0000 0010
3 Channels
0000 0011
4 Channels
0000 0100
5 Channels
0000 0101
...
...
...
...
253 Channels
1111 1101
254 Channels
1111 1110
255 Channels
1111 1111
Table 20 - Local Input Channel Delay Programming Table
LIDRn Bit
(where n = 0
to 31)
Name
Reset
Description
15-5
Reserved
0
Reserved
4-0
LIDn(4:0)
0
Local Input Bit Delay Register
The binary value of these bits refers to the input bit delay value
for the local input stream
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