參數(shù)資料
型號(hào): MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 21/76頁
文件大?。?/td> 1316K
代理商: MT90869AG
Data Sheet
MT90869
21
Zarlink Semiconductor Inc.
Examples are presented, with reference to Table 2:
(3) With stream
LSTo4
selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit for
Channel 0
will be transmitted during the
C16o
clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
(4) With stream
LSTo8
operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1
will
be transmitted during the
C16o
clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus mode) shows the channel control bits
for
LCSTo0
,
LCSTo1
,
LCSTo2
and
LCSTo3
in one possible scenario which includes stream
LSTo0
at a data-rate
of 16.384Mb/s,
LSTo1
at 8.192Mb/s,
LSTo6
at 4.096Mb/s and
LSTo7
at 2.048Mb/s. All remaining streams are
operated at a data-rate of 16.384Mb/s.
4.1.2
LORS Set HIGH
The Local Output Enable Bit (
LE
) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams,
LSTo0-31
. Programming a LOW state will set the stream output of
the MT90869 to High Impedance for the duration of the channel period. See Section 12.3, Local Connection
Memory Bit Definition, for programming details.
The
LCSTo0-3
outputs remain active.
Allocated Stream No.
Channel No.
2
C16o
Period
1
LCSTo0
LCSTo1
LCSTo2
LCSTo3
16Mb/s
8Mb/s
4Mb/s
2Mb/s
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
0
3-1
4
3-3
8
12
16
20
24
28
3-2
0
4
3-3
1
5
9
2
6
3
7
11
15
19
23
27
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 1
Ch 1
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
10
14
18
22
26
13
17
21
25
29
3-2
1
5
30
3-2
2
6
31
3-2
3
7
Frame
1
2
3
4
5
6
7
8
9
8
9
10
14
18
22
26
30
2
6
10
14
18
22
26
30
2
6
10
etc
etc
etc
30
2
6
11
15
19
23
27
31
3
7
11
15
19
23
27
31
3
7
11
etc
etc
etc
31
3
7
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 2
Ch 2
Ch 2
Ch 2
Ch 2
Ch 2
Ch 2
Ch 2
Ch 3
Ch 3
Ch 3
etc
etc
Ch 254
Ch 254
Ch 255
Ch 255
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
Ch 1
etc
etc
Ch 127
Ch 127
Ch 127
Ch 127
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
etc
etc
Ch 63
Ch 63
Ch 63
Ch 63
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
Ch 0
etc
etc
Ch 31
Ch 31
Ch 31
Ch 31
Boundary
12
16
20
24
28
0
4
3-3
8
3-4
12
16
20
24
28
0
4
3-3
8
3-4
etc
etc
etc
28
0
4
13
17
21
25
29
1
5
9
13
17
21
25
29
1
5
9
etc
etc
etc
29
1
5
10
11
12
13
14
15
16
17
etc
etc
2029
2030
2031
2032
Table 2 - LCSTo Allocation of Channel Control Bits to the Output Streams
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