參數(shù)資料
型號: MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 70/76頁
文件大?。?/td> 1316K
代理商: MT90869AG
MT90869
Data Sheet
70
Zarlink Semiconductor Inc.
Figure 25 - GCI BUS Backplane Data Timing Diagram (32Mb/s, 16Mb/s)
Local Clock Data Timing
Characteristic
Sym
Min
Typ
Max
Units
Notes
1
Local Frame Boundary Offset
t
LFBOS
7.5
ns
2
Input data sampling point
t
LIDS16
t
LIDS8
t
LIDS4
t
LIDS2
41
87
178
361
46
92
183
366
51
97
188
371
ns
With zero
offset.
3
Local Serial Input Set-up Time
t
LSIS16
t
LSIS8
t
LSIS4
t
LSIS2
2.1
2.1
2.1
2.1
ns
4
Local Serial Input Hold Time
t
LSIH16
t
LSIH8
t
LSIH4
t
LSIH2
3
3
3
3
ns
5
Local Serial Output Delay
t
LSOD16
t
LSOD8
t
LSOD4
t
LSOD2
0
0
0
0
10.5
10.5
10.5
10.5
ns
C
L
=50pF
CK_int *
FP8i
C8i
BSTi0 - 15
32.768Mb/s
BSTo0 - 15
32.768Mb/s
t
BIDS32
t
BSIS32
t
BIDS16
t
BSIH32
t
BSIH16
t
BSIS16
t
BSOD16
t
BSOD32
BSTo0 - 31
16.384Mb/s
BSTi0 - 31
16.384Mb/s
Bit7
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit1
Bit0
Ch0
Bit6
Bit7
Ch511
Bit2
Ch0
Bit3
Bit4
Ch0
Bit5
6
5
0
4
3
2
1
7
* CK_int is the internal clock signal of 131.072MHz
2
Bit5
Bit6
Ch255
Bit7
Ch255
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