參數(shù)資料
型號： MT90869AG
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 16K Digital Switch (F16kDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝： 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù)： 27/76頁
文件大?。?/td> 1316K
代理商： MT90869AG
Data Sheet
MT90869
27
Zarlink Semiconductor Inc.
The
BCSTo0-3
outputs transmit serial data (channel control bits) at 16.384Mb/s, with each bit representing the per-
channel high impedance state for specific streams. Four output streams are allocated to each control line as
follows:-
(See also
Pin Description
)
BCSTo0 outputs the channel control bits for streams BSTo0, 4, 8, and 12.
BCSTo1 outputs the channel control bits for streams BSTo1, 5, 9, and 13.
BCSTo2 outputs the channel control bits for streams BSTo2, 6, 10, and 14.
BCSTo3 outputs the channel control bits for streams BSTo3, 7, 11, and 15.
The Channel Control Bit location, within a frame period, for each channel of the Backplane output streams is
presented in
Table 4, BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode)
The
BCSTo0-3
outputs data at a constant data-rate of 16.384Mb/s and all output streams,
BSTo0-15
, operate at
a data-rate of 32.768Mb/s.
As an aid to the description, the channel control bit for a single channel on specific streams is presented, with
reference to Table 4:
(1) The Channel Control Bit corresponding to Stream 0, Channel 0,
BSTo0_Ch0,
is transmitted on
BCSTo0
and is
advanced, relative to the Frame Boundary, by six periods (clock period no. 2043) of
C16o
.
(2) The Channel Control Bit corresponding to Stream 12, Channel 0,
BSTo12_Ch0,
is transmitted on
BCSTo0
in
advance of the Frame Boundary by three periods (clock period no. 2046) of output clock,
C16o
. Similarly, the
Channel Control Bits for
BSTo13_Ch0
,
BSTo14_Ch0
and
BSTo15_Ch0
are advanced relative to the Frame
Boundary by three periods of
C16o
, on
BCSTo1
,
BCSTo2
and
BCSTo3
, respectively.
(3) For stream
BSTo4
the value of the Channel Control Bit for
Channel 510
will be transmitted during the
C16o
clock period no. 2036 on
BCSTo0
.
(4) For stream
BSTo5
the value of the Channel Control Bit for
Channel 4
will be transmitted during the
C16o
clock
period no. 12 on
BCSTo1
.
Figure 15, Backplane Port External High Impedance Control Timing (32Mb/s Mode) shows the channel control bits
for
BCSTo0
,
BCSTo1
,
BCSTo2
and
BCSTo3
.
Allocated Stream No.
Channel No.
2
C16o
Period
1
BCSTo0
BCSTo1
BCSTo2
BCSTo3
32Mb/s
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
0
4
8
1
5
9
2
6
3
7
11
15
3
7
11
Ch 511
Ch 511
Ch 511
Ch 511
Ch 0
Ch 0
Ch 0
Ch 0
Ch 1
Ch 1
10
14
2
6
10
12
0
3-1
4
8
12
3-2
0
4
13
1
5
9
13
3-2
1
5
14
3-2
2
6
15
3-2
3
7
Frame
1
2
3
4
5
8
9
10
14
2
6
10
11
15
3
7
11
Ch 1
Ch 1
Ch 2
Ch 2
Ch 2
Boundary
12
0
4
8
13
1
5
9
Table 4 - BCSTo Allocation of Channel Control Bits to the Output Streams (32Mb/s Mode)
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