參數(shù)資料
型號: MT90869AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 16K Digital Switch (F16kDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA272
封裝: 27 X 27 MM, 1.27 MM PITCH, PLASTIC, MS-034-BAL-2, BGA-272
文件頁數(shù): 47/76頁
文件大小: 1316K
代理商: MT90869AG
Data Sheet
MT90869
47
Zarlink Semiconductor Inc.
13.4
Local Input Channel Delay Registers (LCDR0 to LCDR31)
Address 0003h to 0022h.
Thirty-two local input channel delay registers (LCDR0 to LCDR31) allow users to program the input channel delay
for the local input data streams LSTi0-31. The possible adjustment is 255 channels and the
LCDR0 to LCDR31
registers are configured as follows:
:
Table 19 - Local Channel Delay Register (LCDRn) Bits
2
SBERRXL
0
Start Bit Error Rate Receiver for Local.
A LOW to HIGH transition enables the Local BER receiver. The receiver
monitors incoming data for reception of the seed value. When detected, the
LOCK state is indicated (LOCKL) and the receiver compares the incoming bits
with the reference generator for bit equality and increments the Local Bit error
Register (LBCR) on each failure. When set LOW, bit comparison is disabled
and the error count is frozen. The error count is stored in the Local Bit Error
Register (LBCR).
1
SBERTXL
0
Start Bit Error Rate Transmitter for Local.
A LOW to HIGH transition enables the Local BER transmission. When set
LOW, transmission is disabled.
0
PRBSL
0
BER Mode Select for Local.
When set HIGH, a PRBS sequence of length 2
23
-1 is selected for the Local
port. When set LOW, a PRBS sequence of length 2
15
-1 is selected for the
Local port.
LCDRn Bit
(where n = 0 to
31)
Name
Reset
Description
15-8
Reserved
0
Reserved
7-0
LCD(7:0)
0
Local Channel Delay Register
The binary value of these bits refers to the channel delay value
for the local input stream.
Bit
Name
RESET
Description
Table 18 - Bit Error Rate Test Control Register (BERCR) Bits (continued)
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