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參數(shù)資料
| 型號(hào)： | MT90866AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 4 K x 2.4 K Channel Digital Switch with H.110 Interface and 2.4 K x 2.4 K Local Switch |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA344 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, MS-034, BGA-344 |
| 文件頁數(shù)： | 33/86頁 |
| 文件大?。?/td> | 701K |
| 代理商： | MT90866AG2 |
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MT90866
Data Sheet
33
Zarlink Semiconductor Inc.
If the primary reference comes back or recovers, the MT90866 makes a
Stratum 4 Enhanced
compatible switch
back to the original primary reference and the system returns to normal operation state.
If necessary, the MT90866 can be prevented from switching back to the original primary reference by programming
the RPS bit in DOM1 register to give preference to the secondary reference.
While in the Primary Master mode, the MT90866 attenuates jitter and wander above 1.52 Hz from the selected
input reference clock and generates all output clocks according to the DPLL jitter transfer function diagram on
Figure 17, "DPLL Jitter Transfer Function Diagram - wide range of frequencies" on page 42 and Figure 18,
"Detailed DPLL Jitter Transfer Function Diagram" on page 43.
For the Primary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 60.
16.1.2 Secondary Master Mode
In the Secondary Master Mode, the MT90866 drives the “B Clocks” (C8_B_io and FRAME_B_io), by locking to the
“A Clocks”. As required by the H.110 standard, the “B Clocks” are edge-synchronous with the “A Clocks”, as long as
jitter on the “A Clocks” meets Telcordia GR-1244-CORE specifications.
If the “A Clocks” become unreliable, system software is notified and the MT90866 continues driving the “B Clocks”
in stable Holdover Mode until it makes a
Stratum 4 Enhanced
compatible switch to the secondary reference
(SEC_REF) for its network timing. The secondary reference can be the local network reference (LREF0-7), the
CTREF1 or the CTREF2. If the “A Clocks” can not recover, the designated secondary master can be promoted to
primary master by system software. This promotion will cause the “B Clocks” to assume the role of the “A Clocks”.
For the Secondary Master mode selection, see Table 22, "MT90866 Mode Selection - By Programming DOM1 and
DOM2 Registers" on page 60.
16.1.3 Slave Mode
In the Slave Mode, the MT90866 is phase locked to the “A Clocks”. If the “A Clocks” become unreliable, the device
goes to stable Holdover Mode until it makes a
Stratum 4 Enhanced
compatible switch to the “B Clocks”. The
MT90866 will perform all required functionality as long as the “A Clocks” and the “B Clocks” conform to the
Telcordia GR-1244-CORE jitter specifications.
In addition, the device can be used to generate a CT reference (CT_REF1 or CT_REF2) from its network
references, LREF0-7.
While the device is in Slave Mode and the “A Clocks” or the “B Clocks” do not recover, then the designated slave
can be promoted to secondary master by system software. In that case, the network reference can be used as the
secondary reference.
Table 22 on page 60 shows how to program the DOM1 and DOM2 registers to enable the Slave mode of the
MT90866.
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