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MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
Chapter 3
The PowerPC Core
3.1
3.1.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.3.1
3.3.3.2
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.3.1
3.5.3.2
3.5.3.3
3.5.3.4
3.5.3.5
3.5.3.6
3.6
PowerPC Architecture Overview .........................................................................3-1
Levels of the PowerPC Architecture................................................................3-3
Features.................................................................................................................3-4
Basic Structure of the Core...................................................................................3-5
Instruction Flow................................................................................................3-6
Basic Instruction Pipeline.................................................................................3-7
Instruction Unit.................................................................................................3-7
Branch Operations........................................................................................3-7
Dispatching Instructions...............................................................................3-9
Register Set...........................................................................................................3-9
Execution Units....................................................................................................3-9
Branch Processing Unit..................................................................................3-10
Integer Unit.....................................................................................................3-10
Load/Store Unit..............................................................................................3-10
Executing Load/Store Instructions.............................................................3-12
Serializing Load/Store Instructions............................................................3-12
Store Accesses............................................................................................3-12
Nonspeculative Load Instructions..............................................................3-12
Unaligned Accesses....................................................................................3-13
Atomic Update Primitives..........................................................................3-13
The MPC850 and the PowerPC Architecture.....................................................3-14
Chapter 4
PowerPC Core Register Set
4.1
4.1.1
4.1.1.1
4.1.1.1.1
4.1.1.1.2
4.1.1.1.3
4.1.1.1.4
4.1.2
4.1.2.1
4.1.2.2
4.1.2.3
4.1.2.3.1
4.1.2.3.2
4.1.3
MPC850 Register Implementation.......................................................................4-1
PowerPC RegistersUser Registers................................................................4-2
PowerPC User-Level Register Bit Assignments..........................................4-2
Condition Register (CR)...........................................................................4-2
Condition Register CR0 Field Definition.................................................4-3
XER..........................................................................................................4-3
Time Base Registers.................................................................................4-4
PowerPC RegistersSupervisor Registers......................................................4-4
DAR, DSISR, and BAR Operation..............................................................4-5
Unsupported Registers .................................................................................4-6
PowerPC Supervisor-Level Register Bit Assignments................................4-6
Machine State Register (MSR) ................................................................4-6
Processor Version Register ......................................................................4-8
MPC850-Specific SPRs....................................................................................4-8