MOTOROLA
Illustrations
xxxix
ILLUSTRATIONS
Figure
Number
Title
Page
Number
15-21
15-22
15-23
15-24
15-25
15-26
15-27
15-28
15-29
GPCM Relaxed Timing Read (ACS = 1x, SCY = 1, CSNT = 0, and TRLX = 1) ...15-22
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 0, TRLX = 1).........15-23
GPCM Relaxed-Timing Write (ACS = 1x, SCY = 0, CSNT = 1, TRLX =1)..........15-24
GPCM Relaxed-Timing Write (ACS = 00, SCY = 0, CSNT = 1, TRLX =1)..........15-24
GPCM Read Followed by Write (EHTR = 0) ..........................................................15-25
GPCM Read Followed by Write (EHTR = 1) ..........................................................15-26
GPCM Read Followed by Read from Different Banks (EHTR = 1)........................15-26
GPCM Read Followed by Read from Same Bank (EHTR = 1)...............................15-27
Asynchronous External Master Configuration for GPCM-Handled Memory
Devices......................................................................................................................15-28
Asynchronous External Master, GPCM-Handled Memory Access Timing
(TRLX = 0)...............................................................................................................15-29
User-Programmable Machine Block Diagram..........................................................15-30
RAM Array Indexing................................................................................................15-31
Memory Periodic Timer Request Block Diagram....................................................15-32
UPM Clock Scheme One (Division Factor = 1).......................................................15-33
UPM Clock Scheme Two (Division Factor = 2) ......................................................15-34
UPM Signals Timing Example One (Division Factor = 1, EBDF = 00)..................15-35
UPM Signals Timing Example Two (Division Factor = 2, EBDF = 01) .................15-35
RAM Array and Signal Generation..........................................................................15-36
The RAM Word........................................................................................................15-37
CSx Signal Selection.................................................................................................15-40
BSx Signal Selection.................................................................................................15-41
Early GPL5 Control..................................................................................................15-42
Address Multiplex Timing........................................................................................15-45
UPM Read Access Data Sampling ...........................................................................15-49
Wait Mechanism Timing for Internal and External Synchronous Masters ..............15-50
Wait Mechanism Timing for an External Asynchronous Master.............................15-51
Synchronous External Master Access.......................................................................15-54
Asynchronous External Master Access ....................................................................15-55
Synchronous External Master Interconnect Example...............................................15-56
Synchronous External Master: Burst Read Access to Page Mode DRAM ..............15-57
Asynchronous External Master Interconnect Example.............................................15-58
Asynchronous External Master Timing Example.....................................................15-59
Page-Mode DRAM Interface Connection ................................................................15-60
Single-Beat Read Access to Page-Mode DRAM......................................................15-62
Single-Beat Write Access to Page Mode DRAM.....................................................15-63
Burst Read Access to Page-Mode DRAM (No LOOP)............................................15-64
Burst Read Access to Page-Mode DRAM (LOOP)..................................................15-65
Burst Write Access to Page-Mode DRAM (No LOOP)...........................................15-66
Burst Write Access to Page-Mode DRAM (LOOP).................................................15-67
Refresh Cycle (CAS before RAS) to Page-Mode DRAM........................................15-68
Exception Cycle........................................................................................................15-69
15-30
15-31
15-32
15-33
15-34
15-35
15-36
15-37
15-38
15-39
15-40
15-41
15-42
15-43
15-44
15-45
15-46
15-47
15-48
15-49
15-50
15-51
15-52
15-53
15-54
15-55
15-56
15-57
15-58
15-59
15-60
15-61