MOTOROLA
Illustrations
xxxvii
ILLUSTRATIONS
Figure
Number
Title
Page
Number
10-26
10-27
10-28
10-29
10-30
10-31
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
12-1
12-2
12-3
12-4
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10
13-11
13-12
13-13
13-14
13-15
13-16
13-17
13-18
13-19
13-20
13-21
13-22
13-23
13-24
13-25
Real-Time Clock Alarm Register (RTCAL).............................................................10-29
Real-Time Clock Alarm Seconds Register (RTSEC)...............................................10-29
Periodic Interrupt Timer Block Diagram..................................................................10-30
Periodic Interrupt Status and Control Register (PISCR)..........................................10-31
PIT Count Register (PITC).......................................................................................10-32
PIT Register (PITR)..................................................................................................10-32
Power-On and Hard Reset Sequence..........................................................................11-4
Soft Reset Sequence....................................................................................................11-5
Reset Status Register (RSR).......................................................................................11-5
Data Bus Configuration Input Circuit.........................................................................11-7
Reset Configuration Sampling for Short PORESET Assertion..................................11-8
Reset Configuration Sampling for Long PORESET Assertion..................................11-8
Reset Configuration Sampling Timing Requirements................................................11-9
Hard Reset Configuration Word.................................................................................11-9
MPC850 Signals Group..............................................................................................12-2
MPC850 Signals and Pin Numbers (Part 1) ...............................................................12-3
MPC850 Signals and Pin Numbers (Part 2) ...............................................................12-4
Three-State Buffers and Active Pull-Up Buffers......................................................12-19
Input Sample Window................................................................................................13-2
MPC850 Bus Signals..................................................................................................13-3
Basic Transfer Protocol...............................................................................................13-6
Basic Flow Diagram of a Single-Beat Read Cycle.....................................................13-7
Basic Timing: Single-Beat Read Cycle, Zero Wait States .........................................13-8
Basic Timing: Single-Beat Read Cycle, One Wait State............................................13-9
Basic Flow of a Single-Beat Write Cycle.................................................................13-10
Basic Timing: Single-Beat Write Cycle, Zero Wait States.......................................13-11
Basic Timing: Single-Beat Write Cycle, One Wait State.........................................13-12
Basic Timing: Single-Beat, 32-Bit Data Write Cycle, 16-Bit Port Size...................13-13
Basic Flow of a Burst-Read Cycle............................................................................13-16
Burst-Read Cycle: 32-Bit Port Size, Zero Wait State...............................................13-17
Burst-Read Cycle: 32-Bit Port Size, One Wait State................................................13-18
Burst-Read Cycle: 32-Bit Port Size, Wait States between Beats..............................13-19
Burst-Read Cycle: 16-Bit Port Size, One Wait State between Beats .......................13-20
Basic Flow of a Burst Write Cycle...........................................................................13-21
Burst-Write Cycle: 32-Bit Port Size, Zero Wait States ............................................13-22
Burst-Inhibit Cycle: 32-Bit Port Size........................................................................13-23
Internal Operand Representation ..............................................................................13-24
Interface to Different Port Size Devices...................................................................13-24
Bus Arbitration Flowchart........................................................................................13-26
Bus Busy (BB) and Transfer Start (TS) Connection Example.................................13-27
Bus Arbitration Timing Diagram..............................................................................13-28
Internal Bus Arbitration State Machine....................................................................13-29
Termination Signals Protocol Basic Connection......................................................13-34