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MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
36.4.1
36.5
36.5.1
36.5.1.1
36.5.1.2
36.5.1.3
36.5.1.4
36.5.1.5
36.5.1.6
Freeze Indication..........................................................................................36-35
Development Support Programming Model.....................................................36-36
Development Support Registers...................................................................36-37
Comparator ADH Value Registers (CMPADCMPH) ...............................36-37
Breakpoint Address Register (BAR)........................................................36-38
Instruction Support Control Register (ICTRL)........................................36-39
Load/Store Support Comparators Control Register (LCTRL1)...............36-40
Load/Store Support AND-OR Control Register (LCTRL2)....................36-41
Breakpoint Counter Value and Control Registers
(COUNTA/COUNTB).........................................................................36-43
Debug Mode Registers.................................................................................36-44
Interrupt Cause Register (ICR).................................................................36-44
Debug Enable Register (DER).................................................................36-46
Development Port Data Register (DPDR)................................................36-47
36.5.2
36.5.2.1
36.5.2.2
36.5.2.3
Chapter 37
IEEE 1149.1 Test Access Port
37.1
37.2
37.3
37.4
37.4.1
37.4.2
37.4.3
37.4.4
37.4.5
37.5
37.6
37.7
Overview ............................................................................................................37-1
TAP Controller...................................................................................................37-2
Boundary Scan Register.....................................................................................37-3
Instruction Register.............................................................................................37-6
EXTEST.........................................................................................................37-6
SAMPLE/PRELOAD.....................................................................................37-6
BYPASS.........................................................................................................37-7
CLAMP ..........................................................................................................37-7
HIDZ ...............................................................................................................37-7
TAP Usage Considerations.................................................................................37-7
Recommended TAP Configuration....................................................................37-8
Motorola MPC850 BSDL Description...............................................................37-8
Appendix A
Byte Ordering
A.1
A.2
A.3
A.4
A.4.1
A.5
A.5.1
A.6
Byte Ordering Overview .....................................................................................A-1
MPC850 Byte-Ordering Mechanisms................................................................A-1
BE Mode..............................................................................................................A-2
TLE Mode............................................................................................................A-2
TLE Mode System Examples..........................................................................A-4
PPC-LE Mode......................................................................................................A-6
I/O Addressing in PPC-LE Mode....................................................................A-8
Setting the Endian Mode Of Operation...............................................................A-8