MOTOROLA
Contents
xv
CONTENTS
Paragraph
Number
Title
Page
Number
14.3.1.1
The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1,
GCLK2) ...............................................................................................14-10
Memory Controller and External Bus Clocks (GCLK1_50,
GCLK2_50, CLKOUT).......................................................................14-11
CLKOUT Special Considerations: 1:2:1 Mode.......................................14-14
The Baud Rate Generator Clock (BRGCLK)..........................................14-14
The Synchronization Clock (SYNCCLK, SYNCCLKS) ........................14-14
The PIT and RTC Clock (PITRTCLK)........................................................14-15
The Time Base and Decrementer Clock (TMBCLK)..................................14-16
Power Distribution...........................................................................................14-16
I/O Buffer Power (VDDH)...........................................................................14-17
Internal Logic Power (VDDL).....................................................................14-18
Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).......................14-18
Keep-Alive Power (KAPWR)......................................................................14-18
Power Control (Low-Power Modes)................................................................14-18
Normal High Mode......................................................................................14-21
Normal Low Mode.......................................................................................14-21
Doze High Mode..........................................................................................14-21
Doze Low Mode...........................................................................................14-22
Sleep Mode...................................................................................................14-23
Deep-Sleep Mode.........................................................................................14-23
Power-Down Mode......................................................................................14-24
Software Initiation of Power-Down Mode, with Automatic Wake-up....14-24
Maintaining the Real-Time Clock (RTC) During Shutdown or
Power Failure.......................................................................................14-25
Register Lock Mechanism: Protecting SIU Registers in Power-Down
Mode....................................................................................................14-26
TMIST: Facilitating Nesting of SIU Timer Interrupts.................................14-26
Clock and Power Control Registers.................................................................14-26
System Clock and Reset Control Register (SCCR) .....................................14-27
PLL, Low-Power, and Reset Control Register (PLPRCR)..........................14-29
14.3.1.2
14.3.1.3
14.3.1.4
14.3.1.5
14.3.2
14.3.3
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.5
14.5.1
14.5.2
14.5.3
14.5.4
14.5.5
14.5.6
14.5.7
14.5.7.1
14.5.7.2
14.5.7.3
14.5.8
14.6
14.6.1
14.6.2
Chapter 15
Memory Controller
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.3.4
Features..............................................................................................................15-1
Basic Architecture..............................................................................................15-4
Chip-Select Programming Common to the GPCM and UPM...........................15-6
Address Space Programming.........................................................................15-7
Register Programming Order.........................................................................15-7
Memory Bank Write Protection.....................................................................15-7
Address Type Protection................................................................................15-7