lvi
MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
TABLES
Table
Number
Title
Page
Number
34-15
34-16
34-17
34-18
34-19
34-20
35-1
35-2
35-3
35-4
xi
36-1
36-2
36-3
36-4
36-5
36-6
36-7
36-8
36-9
36-10
36-11
36-12
36-13
36-14
36-15
36-16
36-17
36-18
36-19
36-20
36-21
36-22
36-23
36-24
36-25
37-1
A-1
A-2
A-3
A-4
A-5
A-6
PCSO Bit Descriptions ..........................................................................................34-16
PCINT Bit Descriptions.........................................................................................34-17
Port D Pin Assignment...........................................................................................34-17
PDDAT Bit Descriptions.......................................................................................34-18
PDDIR Bit Descriptions ........................................................................................34-19
PDPAR Bit Descriptions........................................................................................34-19
Prioritization of CPM Interrupt Sources..................................................................35-3
Interrupt Vector Encodings......................................................................................35-6
CICR Field Descriptions..........................................................................................35-7
CIVR Field Descriptions........................................................................................35-10
Acronyms and Abbreviated Terms................................................................................VI-ii
Fetch Show Cycles Control .....................................................................................36-3
Status Pin Groupings................................................................................................36-3
VF Pins Encoding: Instruction Queue Flushes........................................................36-4
VF Pins Encoding: Instruction Fetch Types............................................................36-4
Detecting the Trace Buffer Start Point.....................................................................36-7
Instruction Watchpoints Programming Options....................................................36-12
Load/Store Data Events.........................................................................................36-14
Load/Store Watchpoints Programming Options....................................................36-14
Checkstop State and Debug Mode.........................................................................36-24
Trap Enable Data Shifted into Development Port Shift Register..........................36-31
Debug Port Command Shifted Into Development Port Shift Register..................36-31
Status/Data Shifted Out of Development Port Shift Register................................36-32
Debug Instructions/Data Shifted Into Development Port Shift Register...............36-33
MPC850-Specific Development Support and Debug SPRs..................................36-36
Development Support/Debug Registers Protection...............................................36-37
CMPADCMPD Field Descriptions ........................................................................36-37
CMPEDCMPF Field Descriptions..........................................................................36-38
CMPGDCMPH Field Descriptions ........................................................................36-38
BAR Field Descriptions.........................................................................................36-39
ICTRL Field Descriptions......................................................................................36-39
LCTRL1 Field Descriptions ..................................................................................36-41
LCTRL2 Field Descriptions ..................................................................................36-42
COUNTA/COUNTB Field Descriptions...............................................................36-44
ICR Field Descriptions ..........................................................................................36-45
DER Field Descriptions.........................................................................................36-46
Instruction Register Decoding.................................................................................37-6
Byte-Ordering Parameters ........................................................................................A-2
TLE 2-bit Munging...................................................................................................A-3
Little-Endian Program/Data Path Between the Register and 32-Bit Memory..........A-5
Little-Endian Program/Data Path Between the Register and 16-Bit Memory..........A-5
Little-Endian Program/Data Path between the Register and 8-Bit Memory ............A-6
PPC-LE 3-bit Munging.............................................................................................A-7