xvi
MPC850 Integrated Communications Microprocessor Users Manual
MOTOROLA
CONTENTS
Paragraph
Number
Title
Page
Number
15.3.5
15.3.6
15.3.7
15.3.8
15.3.9
15.4
15.4.1
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.4.7
15.4.8
15.5
15.5.1
15.5.1.1
15.5.1.2
15.5.1.3
15.5.1.4
15.5.1.5
15.5.1.6
15.5.2
15.5.3
15.5.4
15.6
15.6.1
15.6.1.1
15.6.1.2
15.6.1.3
15.6.1.4
15.6.2
15.6.3
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.4.4
15.6.4.5
15.6.4.6
15.6.4.7
15.6.4.8
15.6.4.9
8-, 16-, and 32-Bit Port Size Configuration ...................................................15-7
Parity Configuration.......................................................................................15-8
Memory Bank Protection Status.....................................................................15-8
UPM-Specific Registers.................................................................................15-8
GPCM-Specific Registers ..............................................................................15-8
Register Descriptions..........................................................................................15-8
Base Registers (BRx) .....................................................................................15-8
Option Registers (ORx)................................................................................15-10
Memory Status Register (MSTAT)..............................................................15-13
Machine A Mode Register/Machine B Mode Registers (MxMR)...............15-13
Memory Command Register (MCR)............................................................15-15
Memory Data Register (MDR).....................................................................15-16
Memory Address Register (MAR)...............................................................15-17
Memory Periodic Timer Prescaler Register (MPTPR) ................................15-17
General-Purpose Chip-Select Machine (GPCM) .............................................15-18
Timing Configuration...................................................................................15-18
Chip-Select Assertion Timing..................................................................15-19
Chip-Select and Write Enable Deassertion Timing .................................15-20
Relaxed Timing........................................................................................15-22
Output Enable (OE) Timing.....................................................................15-25
Programmable Wait State Configuration.................................................15-25
Extended Hold Time on Read Accesses...................................................15-25
Boot Chip-Select Operation .........................................................................15-27
External Asynchronous Master Support.......................................................15-28
Special Case: Bursting with External Transfer Acknowledge:....................15-29
User-Programmable Machines (UPMs) ...........................................................15-30
Requests........................................................................................................15-31
Internal/External Memory Access Requests ............................................15-31
UPM Periodic Timer Requests.................................................................15-32
Software RequestsMCR run Command...............................................15-32
Exception Requests ..................................................................................15-32
Programming the UPM.................................................................................15-33
Control Signal Generation Timing...............................................................15-33
The RAM Array ...........................................................................................15-36
RAM Words.............................................................................................15-36
Chip-Select Signals (CSTx) .....................................................................15-40
Byte-Select Signals (BSTx)......................................................................15-40
General-Purpose Signals (GxTx, G0x) ....................................................15-41
Loop Control (LOOP)..............................................................................15-43
Exception Pattern Entry (EXEN).............................................................15-44
Address Multiplexing (AMX)..................................................................15-44
Transfer Acknowledge and Data Sample Control (UTA, DLT3)............15-48
Disable Timer Mechanism (TODT).........................................................15-49