參數(shù)資料
型號： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號處理器
文件頁數(shù)： 6/88頁
文件大小： 983K
代理商： MNSC140CORE
MSC8122 Technical Data, Rev. 13
vi
Freescale Semiconductor
Features
Ethernet Controller
Designed to comply with
IEEE
Std 802 including Std. 802.3, 802.3u, 802.3x, and 802.3ac.
Three Ethernet physical interfaces:
—10/100 Mbps MII.
—10/100 Mbps RMII.
—10/100 Mbps SMII.
Full and half-duplex support.
Full-duplex flow control (automatic PAUSE frame generation or software programmed PAUSE frame generation
and recognition).
Out-of-sequence transmit queue for initiating flow-control.
Programmable maximum frame length supports jumbo frames (up to 9.6k) and virtual local area network (VLAN)
tags and priority.
Retransmission from transmit FIFO following a collision.
CRC generation and verification of inbound/outbound packets.
Address recognition:
—Each exact match can be programmed to be accepted or rejected.
—Broadcast address (accept/reject).
—Exact match 48-bit individual (unicast) address.
—Hash (256-bit hash) check of individual (unicast) addresses.
—Hash (256-bit hash) check of group (multicast) addresses.
—Promiscuous mode.
Pattern matching:
—Up to 16 unique 4-byte patterns.
—Pattern match on bit-basis.
—Matching range up to 256 bytes deep into the frame.
—Offsets to a maximum of 252 bytes.
—Programmable pattern size in 4-byte increments up to 64 bytes.
—Accept or reject frames if a match is detected.
—Up to eight unicast addresses for exact matches.
—Pattern matching accepts/rejects IP addresses.
Filing of receive frames based on pattern match; prioritization of frames.
Insertion with expansion or replacement for transmit frames; VLAN tag insertion.
RMON statistics.
Master DMA on the local bus for fetching descriptors and accessing the buffers.
Ethernet PHY can be exposed either on GPIO pins or on the high most significant bits of the DSI/system when
the DSI and the system bus are both 32 bits.
MPC8260 8-byte width buffer descriptor mode as well as 32 byte width buffer descriptor mode.
MII Bridge (MIIGSK):
—Programmable selection of the 50 MHz RMII reference clock source (external or internal).
—Independent 2 bit wide transmit and receive data paths.
—Six operating modes.
—Four general-purpose control signals.
—Programmable transmitted inter-frame bits to support inter-frame gap for frames in the SMII domain.
SMII features:
—Multiplexed only with GPIO signals
—Convey complete MII information between the PHY and MAC.
—Allow direct MAC-to-MAC communication in SMII mode.
—Can generate an interrupt request line while receiving inter-frame segments.
Feature
Description
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