參數(shù)資料
型號： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號處理器
文件頁數(shù)： 31/88頁
文件大?。?/td> 983K
代理商： MNSC140CORE
GPIO, TDM, UART, and Timer Signals
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-21
GPIO18
TDM1RSYN
DREQ2
Input/ Output
Input/ Output
Input
General-Purpose Input Output 18
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122 Reference Manual
GPIO programming model.
TDM1 Receive Frame Sync
The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For
configuration details, refer to the
MSC8122
Reference Manual
.
DMA Request 1
Used by an external peripheral to request DMA service.
GPIO19
TDM1RCLK
DACK2
Input/ Output
Input/ Output
Output
General-Purpose Input Output 19
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
TDM1 Receive Clock
The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For
configuration details, refer to the
MSC8122
Reference Manual
chapter describing TDM operation.
DMA Acknowledge 2
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
GPIO20
TDM1RDAT
Input/ Output
Input/ Output
General-Purpose Input Output 20
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
TDM1 Serial Receiver Data
The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For
configuration details, refer to the
MSC8122
Reference Manual
.
GPIO21
TDM0TSYN
Input/ Output
Input/ Output
General-Purpose Input Output 21
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
TDM0 Transmit frame Sync
Transmit Frame Sync for TDM 0.
GPIO22
TDM0TCLK
DONE2
DRACK2
Input/ Output
Input
Input/ Output
Output
General-Purpose Input Output 22
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For
details, refer to the
MSC8122 Reference Manual
GPIO programming model.
TDM 0 Transmit Clock
Transmit Clock for TDM 0.
DMA Done 2
Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this
peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel
closing.
Note:
See the
MSC8122 Reference Manual
chapters on DMA and GPIO for information on
configuring the DRACK or DONE mode and pin direction.
DMA Data Request Acknowledge 2
Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request.
Table 1-7.
GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
Type
Description
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