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參數(shù)資料
| 型號： | MNSC140CORE |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 50/88頁 |
| 文件大?。?/td> | 983K |
| 代理商： | MNSC140CORE |
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MSC8122 Technical Data, Rev. 13
2-16
Freescale Semiconductor
Specifications
2.5.6
The timings in the following sections are based on a 20 pF capacitive load.
DSI Timing
2.5.6.1 DSI Asynchronous Mode
Table 2-17.
DSI Asynchronous Mode Timing
No.
Characteristics
Min
Max
Unit
100
101
102
Attributes
1
set-up time before strobe (HWBS[n]) assertion
Attributes
1
hold time after data strobe deassertion
Read/Write data strobe deassertion width:
DCR[HTAAD] = 1
— Consecutive access to the same DSI
— Different device with DCR[HTADT] = 01
— Different device with DCR[HTADT] = 10
— Different device with DCR[HTADT] = 11
DCR[HTAAD] = 0
Read data strobe deassertion to output data high impedance
Read data strobe assertion to output data active from high impedance
Output data hold time after read data strobe deassertion
Read/Write data strobe assertion to HTA active from high impedance
Output data valid to HTA assertion
Read/Write data strobe assertion to HTA valid
2
1.1 V core
1.2 V core
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 0, HTA at end of access released at logic 0)
Read/Write data strobe deassertion to output HTA deassertion.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1)
Read/Write data strobe deassertion to output HTA high impedance.
(DCR[HTAAD] = 1, HTA at end of access released at logic 1
DCR[HTADT] = 01
DCR[HTADT] = 10
DCR[HTADT] = 11
Read/Write data strobe assertion width
Host data input set-up time before write data strobe deassertion
Host data input hold time after write data strobe deassertion
1.1 V core
1.2 V core
1.
Attributes
refers to the following signals: HCS, HA[11–29], HCID[0–4], HDST, HRW, HRDS, and HWBSn.
2.
This specification is tested in dual-strobe mode. Timing in single-strobe mode is guaranteed by design.
3.
All values listed in this table are tested or guaranteed by design.
1.5
1.3
—
—
—
ns
ns
1.8 + T
REFCLK
5 + T
REFCLK
5 + (1.5
×
T
REFCLK
)
5 + (2.5
×
T
REFCLK
)
1.8 + T
REFCLK
—
2.0
2.2
2.2
3.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
103
104
105
106
107
108
8.5
—
—
—
—
—
—
—
7.4
6.7
6.5
ns
ns
ns
109
110
—
6.5
ns
111
—
5 + T
REFCLK
5 + (1.5
×
T
REFCLK
)
5 + (2.5
×
T
REFCLK
)
—
—
ns
ns
ns
ns
ns
112
201
202
1.8 + T
REFCLK
1.0
1.7
1.5
—
—
ns
ns
Notes:
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| MO1101A | 1.02 SINGLE DIGIT NUMERIC DISPLAY |
| MO1101C | 1.02 SINGLE DIGIT NUMERIC DISPLAY |
| MO1145C | Peripheral IC |
| MO1146C | Peripheral IC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MNSC140CORE/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MNSCAN18541T-X | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SERIALLY CONTROLLED ACCESS NETWORK NON-INVERTING LINE DRIVER WITH TRI-STATE OUTPUTS |
| M-NSD10 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
| M-NSD16 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
| M-NSD20 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
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