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參數(shù)資料
| 型號： | MNSC140CORE |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 45/88頁 |
| 文件大小： | 983K |
| 代理商： | MNSC140CORE |
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AC Timings
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
2-11
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller
configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only
on the
REFCLK
rising edge.
Table 2-13.
AC Timing for SIU Inputs
No.
Characteristic
Value for Bus Speed in MHz
Units
Ref = CLKIN
Ref = CLKOUT
1.1 V
1.2 V
1.2 V
1.2 V
100/
133
133
166
133
10
Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
0.5
0.5
0.5
ns
11a
ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge
3.1
3.0
3.0
3.0
ns
11b
DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK
rising edge
3.6
3.3
3.3
3.3
ns
11c
AACK set-up time before the 50% level of the REFCLK rising edge
3.0
2.9
2.9
2.9
ns
11d
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
Data-pipeline mode
Non-pipeline mode
3.5
4.4
3.4
4.0
3.4
4.0
3.4
4.0
ns
ns
12
Data bus set-up time before REFCLK rising edge in Normal mode
Data-pipeline mode
Non-pipeline mode
1.9
4.2
1.8
4.0
1.7
4.0
1.8
4.0
ns
ns
13
1
Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
Data-pipeline mode
Non-pipeline mode
2.0
8.2
2.0
7.3
2.0
7.3
2.0
7.3
ns
ns
14
1
DP set-up time before the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
2.0
7.9
2.0
6.1
2.0
6.1
2.0
6.1
ns
ns
15a
TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
4.2
5.5
3.8
5.0
3.8
5.0
3.8
5.0
ns
ns
15b
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.7
4.8
3.5
4.4
3.5
4.4
3.5
4.4
ns
ns
16
PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge
IRQx setup time before the 50% level; of the REFCLK rising edge
3
IRQx minimum pulse width
3
3.7
3.7
3.7
3.7
ns
17
4.0
4.0
4.0
4.0
ns
18
6.0 +
T
REFCLK
6.0 +
T
REFCLK
6.0 +
T
REFCLK
6.0 + T
REFCLK
ns
Notes:
1.
2.
3.
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
Guaranteed by design.
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