參數(shù)資料
型號(hào)： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 33/88頁(yè)
文件大?。?/td> 983K
代理商： MNSC140CORE
Dedicated Ethernet Signals
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-23
1.7 Dedicated Ethernet Signals
Most Ethernet signals are multiplexed with the DSI/system bus and the GPIO ports. In addition to the multiplexed
signals, there are three dedicated Ethernet signals that are described in
Table 1-8.
GPIO29
CHIP_ID3
ETHTX_EN
Input/ Output
Input
Output
General-Purpose Input Output 29
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
Chip ID 3
Determines the chip ID of the MSC8122 DSI. It is sampled on the rising edge of PORESET signal.
Ethernet Transmit Enable
Used to enable the Ethernet transmit controller for MII and RMII modes.
GPIO30
TIMER2
TMCLK
SDA
Input/ Output
Input/ Output
Input
Input/ Output
General-Purpose Input Output 30
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
Timer
2
Each signal is configured as either input to the counter or output from the counter. For the configuration of
the pin direction, refer to the
MSC8122 Reference Manual
.
External TIMER Clock
An external timer can connect directly to the SIU as the SIU clock.
I
2
C-Bus Data Line
This is the data line for the I
2
C bus.
GPIO31
TIMER3
SCL
Input/ Output
Input/ Output
Input/ Output
General-Purpose Input Output 31
One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For
details, refer to the
MSC8122
Reference Manual
GPIO programming model.
Timer
3
Each signal is configured as either input to or output from the counter. For the configuration of the pin
direction, refer to the
MSC8122 Reference Manual
.
I
2
C-Bus Clock Line
This the clock line for the I
2
C bus.
Table 1-8.
Dedicated Ethernet Signals
Signal Name
Type
Signal Description
ETHRX_CLK
ETHSYNC_IN
Input
Input
Receive Clock
In MII mode, provides the timing reference for the receive signals.
Sync Input
In SMII mode, is the sync signal input line.
ETHTX_CLK
ETHREF_CLK
ETHCLOCK
Input
Input
Input
Transmit Clock
In MII mode, provides the timing reference for transmit signals.
Reference Clock
In RMII mode, provides the timing reference.
Ethernet Clock
In SMII mode, provides the Ethernet clock signal.
Table 1-7.
GPIO, TDM, UART, Ethernet, and Timer Signals (Continued)
Signal Name
Type
Description
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