MSC8122 Technical Data, Rev. 13
1-2
Freescale Semiconductor
Signals/Connections
HD0/SWTE
HD1/DSISYNC
HD2/DSI64
HD3/MODCK1
HD4/MODCK2
HD5/CNFGS
HD[6–31]
→
→
→
→
1
1
1
1
1
1
26
8
1
1
1
1
2
1
1
1
1
4
1
1
1
1
1
1
1
3
3
1
19
4
4
D
S
I
/
S
Y
S.
B
U
S
/
E
T
H
E
R
N
E
T
S
Y
S
T
E
M
B
U
S
32
A[0–31]
1
TT0/HA7
1
TT1
3
TT[2–4]/CS[5–7]
5
→
CS[0–4]
4
TSZ[0–3]
1
TBST
1
IRQ1
/GBL
1
IRQ3
/BADDR31
1
IRQ2
/BADDR30
1
IRQ5
/BADDR29
1
→
BADDR28
1
→
BADDR27
1
BR
1
BG
1
DBG
1
ABB
/IRQ4
1
DBB
/IRQ5
1
TS
1
AACK
1
ARTRY
32
D[0–31]
1
reserved/DP0/DREQ1/EXT_BR2
1
IRQ1
/DP1/DACK1/EXT_BG2
1
IRQ2
/DP2/DACK2/EXT_DBG2
1
IRQ3
/DP3/DREQ2/EXT_BR3
1
IRQ4
/DP4/DACK3/EXT_DBG3
1
IRQ5
/DP5/DACK4/EXT_BG3
1
IRQ6
/DP6/DREQ3
1
IRQ7
/DP7/DREQ4
1
TA
HD[32-39]/D[32-39]/reserved
HD40/D40/ETHRXD0
HD41/D41/ETHRXD1
HD42/D42/ETHRXD2/reserved
HD43/D43/ETHRXD3/reserved
HD[44-45]/D[44-45]/reserved
HD46/D46/ETHTXD0
HD47/D47/ETHTXD1
HD48/D48/ETHTXD2/reserved
HD49/D49/ETHTXD3/reserved
HD[50-53]/D[50-53]/reserved
HD54/D54/ETHTX_EN
HD55/D55/ETHTX_ER/reserved
HD56/D56/ETHRX_DV/ETHCRS_DV
HD57/D57/ETHRX_ER
HD58/D58/ETHMDC
HD59/D59/ETHMDIO
HD60/D60/ETHCOL/reserved
HD[61–63]/D[61-63]/reserved
HCID[0–2]
HCID3/HA8
HA[11–29]
M
E
M
C
D
S
I
HWBS[0–3]/HDBS[0–3]/HWBE[0–3]/HDBE[0–3]
HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/
PWE[4–7]/PSDDQM[4–7]/PBS[4–7]
HRDS/HRW/HRDE
→
→
→
→
→
←
→
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
4
1
1
1
1
1
1
TEA
←
NMI
→
NMI_OUT
PSDVAL
IRQ7
/
INT_OUT
→
BCTL0
→
BCTL1
/CS5
BM[0–2]/TC[0–2]/BNKSEL[0–2]
→
ALE
→
PWE[0–3]
/PSDDQM[0–3]/PBS[0–3]
→
PSDA10/PGPL0
→
PSDWE
/PGPL1
→
POE
/PSDRAS/PGPL2
→
PSDCAS
/PGPL3
PGTA
/PUPMWAIT/PGPL4/PPBS
→
PSDAMUX/PGPL5
HBRST
HDST[0–1]/HA[9–10]
HCS
HBCS
HTA
HCLKIN
M
E
M
C
S
Y
S
GPIO0/CHIP_ID0/IRQ4/ETHTXD0
GPIO1/TIMER0/CHIP_ID1/IRQ5/ETHTXD1
GPIO2/TIMER1/CHIP_ID2/IRQ6
GPIO3/TDM3TSYN/IRQ1/ETHTXD2
GPIO4/TDM3TCLK/IRQ2/ETHTX_ER
GPIO5/TDM3TDAT/IRQ3/ETHRXD3
GPIO6/TDM3RSYN/IRQ4/ETHRXD2
GPIO7/TDM3RCLK/IRQ5/ETHTXD3
GPIO8/TDM3RDAT/IRQ6/ETHCOL
GPIO9/TDM2TSYN/IRQ7/ETHMDIO
GPIO10/TDM2TCLK/IRQ8/ETHRX_DV/ETHCRS_DV/NC
GPIO11/TDM2TDAT/IRQ9/ETHRX_ER/ETHTXD
GPIO12/TDM2RSYN/IRQ10/ETHRXD1/ETHSYNC
GPIO13/TDM2RCLK/IRQ11/ETHMDC
GPIO14/TDM2RDAT/IRQ12/ETHRXD0/NC
GPIO15/TDM1TSYN/DREQ1
GPIO16/TDM1TCLK/DONE1/DRACK1
GPIO17/TDM1TDAT/DACK1
GPIO18/TDM1RSYN/DREQ2
GPIO19/TDM1RCLK/DACK2
G
P
I
O
/
T
D
M
/
E
T
H
E
R
N
E
T
/
T
I
M
E
R
S
/
I
2
C
De
bug
C
L
K
R
E
S
E
T
J
T
A
G
1
1
1
1
1
1
1
1
1
1
1
1
1
1
←
EE0
→
EE1
→
CLKOUT
←
Reserved
←
CLKIN
←
PORESET
HRESET
SRESET
←
RSTCONF
←
TMS
←
TDI
←
TCK
←
TRST
→
TDO
GPIO20/TDM1RDAT
GPIO21/TDM0TSYN
GPIO22/TDM0TCLK/DONE2/DRACK2
GPIO23/TDM0TDAT/IRQ13
GPIO24/TDM0RSYN/IRQ14
GPIO25/TDM0RCLK/IRQ15
GPIO26/TDM0RDAT
GPIO27/URXD/DREQ1
GPIO28/UTXD/DREQ2
GPIO29/CHIP_ID3/ETHTX_EN
GPIO30/TIMER2/TMCLK/SDA
GPIO31
/
TIMER3/SCL
Ded.
Eth.
Net
1
1
1
←
ETHRX_CLK/ETHSYNC_IN
←
ETHTX_CLK/ETHREF_CLK/ETHCLOCK
←
ETHCRS/ETHRXD
Power signals are: V
DD
, V
DDH
, V
CCSYN
, GND, GND
H
, and GND
SYN
. Reserved signals can be left unconnected. NC signals must not be connected.
Figure 1-1.
MSC8122 External Signals