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參數(shù)資料
| 型號： | MNSC140CORE |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 42/88頁 |
| 文件大?。?/td> | 983K |
| 代理商： | MNSC140CORE |
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MSC8122 Technical Data, Rev. 13
2-8
Freescale Semiconductor
Specifications
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting
PORESET
initiates the power-on reset flow.
PORESET
must be asserted externally for at least 16
CLKIN
cycles after
V
DD
and
V
DDH
are both at their nominal levels.
2.5.4.2 Reset Configuration
The MSC8122 has two mechanisms for writing the reset configuration:
Through the direct slave interface (DSI)
Through the system bus. When the reset configuration is written through the system bus, the MSC8122
acts as a configuration master or a configuration slave. If configuration slave is selected, but no special
configuration word is written, a default configuration word is applied.
Fourteen signal levels (see
Chapter 1
for signal description details) are sampled on
PORESET
deassertion to define
the Reset Configuration Mode and boot and operating conditions:
RSTCONF
CNFGS
DSISYNC
DSI64
CHIP_ID[0–3]
BM[0–2]
SWTE
MODCK[1–2]
Table 2-10.
Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On
Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog or
Bus Monitor)
External
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.5.4.1
for details)
.
SPLL state reset
System reset configuration write through
the DSI
System reset configuration write though
the system bus
HRESET driven
SIU registers reset
IPBus modules reset (TDM, UART,
Timers, DSI, IPBus master, GIC, HS, and
GPIO)
SRESET driven
SC140 extended cores reset
MQBS reset
Yes
No
No
No
Yes
Yes
No
No
No
No
No
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Depends on command
Yes
Yes
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