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參數(shù)資料
| 型號： | MNSC140CORE |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Quad Core 16-Bit Digital Signal Processor |
| 中文描述： | 四核16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 23/88頁 |
| 文件大?。?/td> | 983K |
| 代理商： | MNSC140CORE |
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Direct Slave Interface, System Bus, Ethernet, and Interrupt Signals
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
1-13
IRQ5
DP5
DACK4
EXT_BG3
Input
Input/ Output
Output
Output
Interrupt Request 5
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 5
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and
D[40–47].
DMA Acknowledge 4
The DMA controller drives this output to acknowledge the DMA transaction on the bus.
External Bus Grant 3
2
The MSC8122 asserts this pin to grant bus ownership to an external bus.
IRQ6
DP6
DREQ3
Input
Input/ Output
Input
Interrupt Request 6
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 6
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and
D[48–55].
DMA Request 3
Used by an external peripheral to request DMA service.
IRQ7
DP7
DREQ4
Input
Input/ Output
Input
Interrupt Request 7
One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the
SC140 core.
System Bus Data Parity 7
The agent that drives the data bus also drives the data parity signals. The value driven on the data parity
7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and
D[56–63].
DMA Request 4
Used by an external peripheral to request DMA service.
TA
Input/ Output
Transfer Acknowledge
Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the
termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight
data beats, with the last assertion indicating the termination of the burst transfer.
TEA
Input/ Output
Transfer Error Acknowledge
Indicates a failure of the data tenure transaction.The masters within the MSC8122 monitor the state of this
pin. The MSC8122 internal bus monitor can assert this pin if it identifies a bus transfer that does not
complete.
NMI
Input
Non-Maskable Interrupt
When an external device asserts this line, it generates an non-maskable interrupt in the MSC8122, which
is processed internally (default) or is directed to an external host for processing (see NMI_OUT).
NMI_OUT
Output
Non-Maskable Interrupt Output
An open-drain pin driven from the MSC8122 internal interrupt controller. Assertion of this output indicates
that a non-maskable interrupt is pending in the MSC8122 internal interrupt controller, waiting to be
handled by an external host.
PSDVAL
Input/ Output
Port Size Data Valid
Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin
is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted
with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when
PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA controller initiates a double
word (2
×
64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times
without TA and, finally, both pins are asserted to terminate the transfer.
Table 1-5.
DSI, System Bus, Ethernet, and Interrupt Signals (Continued)
Signal Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MO1101A | 1.02 SINGLE DIGIT NUMERIC DISPLAY |
| MO1101C | 1.02 SINGLE DIGIT NUMERIC DISPLAY |
| MO1145C | Peripheral IC |
| MO1146C | Peripheral IC |
| XO1146C | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MNSC140CORE/D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor |
| MNSCAN18541T-X | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SERIALLY CONTROLLED ACCESS NETWORK NON-INVERTING LINE DRIVER WITH TRI-STATE OUTPUTS |
| M-NSD10 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
| M-NSD16 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
| M-NSD20 | 制造商:COOPER 制造商全稱:Cooper Bussmann, Inc. 功能描述:6 Reasons To Order Our Exciting New Cooper Bussmann Packaging |
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