參數(shù)資料
型號(hào)： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 44/88頁(yè)
文件大小： 983K
代理商： MNSC140CORE
MSC8122 Technical Data, Rev. 13
2-10
Freescale Semiconductor
Specifications
2.5.5
System Bus Access Timing
2.5.5.1 Core Data Transfers
Generally, all MSC8122 bus and system output signals are driven from the rising edge of the reference clock
(REFCLK). The REFCLK is the
CLKIN
signal. Memory controller signals, however, trigger on four points within a
REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge of REFCLK (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio
selected, as
Table 2-12
shows.
Figure 2-5
is a graphical representation of
Table 2-12
.
Table 2-12.
Tick Spacing for Memory Controller Signals
BCLK/SC140 clock
Tick Spacing (T1 Occurs at the Rising Edge of REFCLK)
T2
T3
T4
1:4, 1:6, 1:8, 1:10
1/4 REFCLK
1/2 REFCLK
3/4 REFCLK
1:3
1/6 REFCLK
1/2 REFCLK
4/6 REFCLK
1:5
2/10 REFCLK
1/2 REFCLK
7/10 REFCLK
Figure 2-5.
Internal Tick Spacing for Memory Controller Signals
REFCLK
T1
T2
T3
T4
REFCLK
T1
T2
T3
T4
for 1:3
for 1:5
REFCLK
T1
T2
T3
T4
for 1:4, 1:6, 1:8, 1:10
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