參數(shù)資料
型號(hào)： MNSC140CORE
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core 16-Bit Digital Signal Processor
中文描述： 四核16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 39/88頁(yè)
文件大?。?/td> 983K
代理商： MNSC140CORE
AC Timings
MSC8122 Technical Data, Rev. 13
Freescale Semiconductor
2-5
2.5.1
Output Buffer Impedances
2.5.2
Starting the device requires coordination among several input sequences including clocking, reset, and power.
Section 2.5.3
describes the clocking characteristics.
Section 2.5.4
describes the reset and power-up characteristics.
You must use the following guidelines when starting up an MSC8122 device:
Start-Up Timing
PORESET
and
TRST
must be asserted externally for the duration of the power-up sequence. See
Table 2-10
for timing.
If possible, bring up the
V
DD
and
V
DDH
levels together. For designs with separate power supplies, bring up
the
V
DD
levels and then the
V
DDH
levels (see
Figure 2-3
).
CLKIN
should start toggling at least 16 cycles (starting after
V
DDH
reaches its nominal level) before
PORESET
deassertion to guarantee correct device operation (see
Figure 2-2
and
Figure 2-3
).
CLKIN
must not be pulled high during
V
DDH
power-up.
CLKIN
can toggle during this period.
The following figures show acceptable start-up sequence examples.
Figure 2-2
shows a sequence in which
V
DD
and
V
DDH
are raised together.
Figure 2-3
shows a sequence in which
V
DDH
is raised after
V
DD
and
CLKIN
begins to toggle
as
V
DDH
rises.
Table 2-5.
Output Buffer Impedances
Output Buffers
Typical Impedance (
Ω
)
System bus
Memory controller
Parallel I/O
Note:
50
50
50
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
Figure 2-2.
Start-Up Sequence with V
DD
and V
DDH
Raised Together
V
Time
o.5 V
3.3 V
1.2 V
V
DDH
Nominal Level
PORESET/TRST Asserted
V
DD
/V
DDH
Applied
V
DD
Nominal Level
CLKIN Starts Toggling
PORESET/TRST Deasserted
1
2.2 V
V
DDH
= Nominal Value
V
DD
= Nominal Value
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