參數(shù)資料
型號(hào)： LQ80221
英文描述： LAN Transceiver
中文描述： 網(wǎng)絡(luò)收發(fā)器
文件頁數(shù)： 41/91頁
文件大?。?/td> 907K
代理商： LQ80221
80220/80221
4-41
MD400159/E
Table 17. MI Register 17 (Configuration 2) Structure And Bit Definition
17.15
PLED3_1
R/W
17.14
PLED3_0
R/W
17.13
PLED2_1
R/W
17.12
PLED2_0
R/W
17.11
PLED1_1
R/W
17.10
PLED1_0
R/W
17.9
17.8
PLED0_1
R/W
PLED0_0
R/W
17.7
17.6
17.5
17.4
17.3
MREG
R/W
17.2
17.1
17.0
0
R/W
LED_DEF1
R/W
LED_DEF0
R/W
APOL_DIS
R/W
JAB_DIS
R/W
INT_MDIO
R/W
P26_CFG
R/W
Bit
17.15
17.14
Symbol
PLED3_1
PLED3_0
Name
Programmable LED
Output Select, Pin
PLED3
Definition
11 = Normal
R/W
R/W
Def.
11
(PLED3 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is LINK100)
(PLED3 Is Toggling 100 mS
Low, 100 mS High)
(PLED3 Is Low)
(PLED3 Is High)
(PLED2 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is Activity)
(PLED2 Is Toggling 100 mS
Low, 100 mS High)
(PLED2 Is Low)
(PLED2 Is High)
(PLED1 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is Full Duplex)
(PLED1 Is Toggling 100 mS
Low, 100 mS High)
(PLED1 Is Low)
(PLED1 Is High)
(PLED0 Is Determined By
Bits 17.7-17.6 And Table 5.
Default is LINK10)
(PLED0 Is Toggling 100 mS
Low, 100 mS High)
(PLED0 Is Low)
(PLED0 Is High)
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
17.13
17.12
PLED2_1
PLED2_0
Programmable LED
Output Select, Pin
PLED2
R/W
11
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
17.11
17.10
PLED1_1
PLED1_0
Programmable LED
Output Select, Pin
PLED1
R/W
11
10 = LED Blink
01 = LED On
00 = LED Off
11 = Normal
17.9
17.8
PLED0_1
PLED0_0
Programmable LED
Output Select, Pin
PLED0
R/W
11
10 = LED Blink
01 = LED On
00 = LED Off
See Table 5
17.7
17.6
17.5
LED_DEF1
LED_DEF0
APOL_DIS
LED Normal
Function Select
Auto Polarity
Disable
Jabber Disable
Select
Multiple Register
Access Enable
Interrupt Scheme
Select
R/J Configuration
Select
R/W
0
1 = Auto Polarity Correction Function Disabled
0 = Normal
1 = Jabber Disabled
0 = Enabled
1 = Multiple Register Access Enabled
0 = No Multiple Register Access
1 = Interrupt Signaled With MDIO Pulse During Idle
0 = Interrupt Not Signalled On MDIO
1 = RX_EN/JAM Pin Is Configured To Be JAM
0 = RX_EN/JAM Pin Is Configured To Be RX_EN
Reserved
R/W
0
17.4
JAB_DIS
R/W
0
17.3
MREG
R/W
0
17.2
INT_MDIO
R/W
0
17.1
R/J_CFG
R/W
0
17.0
R/W
0
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