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參數(shù)資料
| 型號： | LQ80221 |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡收發(fā)器 |
| 文件頁數(shù)： | 28/91頁 |
| 文件大?。?/td> | 907K |
| 代理商： | LQ80221 |
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80220/80221
MD400159/E
28
on reset nterval, the value on these pins s atched nto the
device, inverted, and used as the MI serial port physical
device addresses.
3.26.2 Timing
A timing diagram for a MI serial port frame is shown in
Figure 9. The MI serial port is idle when at least 32
continuous 1's are detected on MDIO and remains idle as
long as continuous 1's are detected. During idle, MDIO is
in the high impedance state. When the MI serial port is in
the dle state, a 01 pattern on the MDIO pin nitiates a serial
shift cycle. Data on MDIO is then shifted in on the next 14
rising edges of MDC (MDIO is high impedance). If the
register access mode is not enabled, on the next 16 rising
edges of MDC, data is either shifted in or out on MDIO,
depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles
have been completed, one complete register has been
read/written, the serial shift process is halted, data is
latched into the device, and MDIO goes into high imped-
ance state. Another serial shift cycle cannot be initiated
until the idle condition (at least 32 continuous 1's) is
detected.
3.26.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial
port access cycle with the multiple register access feature.
The multiple register access feature can be enabled by
setting the multiple register access enable bit in the MI
serial port Configuration 2 register. When multiple register
access is enabled, multiple registers can be accessed on
a single MI serial port access cycle by setting the register
address to 11111 during the first 16 MDC clock cycles.
There is no actual register residing in register address
location 11111, so when the register address s then set to
11111, all eleven registers are accessed on the 176 rising
edges of MDC that occur after the first 16 MDC clock
cycles of the MI serial port access cycle. The registers are
accessed in numerical order from 0 to 20. After all 192
MDC clocks have been completed, all the registers have
been read/written, and the serial shift process is halted,
data is latched into the device, and MDIO goes into high
impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's)
is detected.
3.26.4 Bit Types
Since the serial port is bidirectional, there are many types
of bits. Write bits (W) are nputs during a write cycle and are
high impedance during a read cycle. Read bits (R) are
outputs during a read cycle and high impedance during a
write cycle. Read/Write bits (R/W) are actually write bits
which can be read out during a read cycle. R/WSC bits are
R/W bits that are self clearing after a set period of time or
after a specific event has completed. R/LL bits are read
bits that atch themselves when they go ow, and they stay
latched low until read. After they are read, they are reset
high. R/LH bits are the same as R/LL bits except that they
latch high. R/LT are read bits that latch themselves
whenever they make a transition or change value, and
they stay latched until they are read. After R/LT bits are
read, they are updated to their current value. R/LT bits can
also be programmed to assert the interrupt function as
described in the Interrupt section. The bit type definitions
are summarized in Table 7.
Table 7. MI Register Bit Type Definition
Sym.
Name
Definition
Write Cycle
Read Cycle
W
Write
Input
No Operation, Hi Z
R
Read
No Operation,
Hi Z
Output
R/W
Read/
Write
Input
Ouput
R/WS
C
Read/
Write Self
Clearing
Input
Ouput
Clears Itself
After Operation
Completed
R/LL
Read/
Latching
Low
No Operation,
Hi Z
Output
When Bit Goes
Low, Bit Latched.
When Bit Is Read,
Bit Updated.
R/LH
Read/
Latching
High
No Operation,
Hi Z
Output
When Bit Goes
High, Bit Latched.
When Bit Is Read,
Bit Updated.
R/LT
Read/
Latching
on
Transition
No Operation,
Hi Z
Output
When Bit
Transitions,
Bit Latched And
Interrupt Set
When Bit Is Read,
Interrupt Cleared
And Bit Updated.
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