- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369830 > LQ80221 LAN Transceiver PDF資料下載
參數(shù)資料
| 型號(hào)： | LQ80221 |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 19/91頁 |
| 文件大?。?/td> | 907K |
| 代理商： | LQ80221 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當(dāng)前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁
80220/80221
4-19
MD400159/E
level MLT-3 digital data from the comparators and con-
verts it to back to normal digital data to be used for clock
and data recovery.
3.9.2 Receiver - 10 Mbps
The 10 Mbps receiver is able to detect input signals from
the twisted pair cable that are within the template shown n
Figure 5. The inputs are biased by internal resistors. The
TP inputs pass through a low pass filter designed to
eliminate any high frequency noise on the input. The
output of the receive filter goes to two different types of
comparators, squelch and zero crossing. The squelch
comparator determines whether he signal s valid, and he
zero crossing comparator is used to sense the actual data
transitions once the signal is determined to be valid. The
output of the squelch comparator goes to the squelch
circuit and is also used for link pulse detection, SOI
detection, and reverse polarity detection; the output of the
zero crossing comparator is used for clock and data
recovery in the Manchester decoder.
3.9.3 TP Squelch - 100 Mbps
The squelch block determines f he TP nput contains valid
data. The 100 Mbps TP squelch is one of the criteria used
to determine link intergrity. The squelch comparators
compare the TP nputs against fixed positive and negative
thresholds, called squelch levels. The output from the
squelch comparator goes to a digital squelch circuit which
determines f he receive nput data on hat channel s valid.
If the data s nvalid, the receiver s n the squelched state.
If the input voltage exceeds the squelch levels at least 4
times with alternating polarity within a 10
μ
S interval, the
data s considered to be valid by the squelch circuit and the
receiver now enters into the unquelch state. In the
unsquelch state, the receive threshold level is reduced by
approximately 30% for noise immunity reasons and is
called the unsquelch level. When the receiver is in the
unsquelch state, then the input signal is deemed to be
valid. The device stays in the unsquelch state until loss of
data is detected. Loss of data is detected if no alternating
polarity unsquelch transitions are detected during any 10
μ
S nterval. When the oss of data s detected, the receive
squelch is turned on again.
3.9.4 TP Squelch, 10 Mbps
The TP squelch algorithm for 10 Mbps mode s dentical to
the 100 Mbps mode except, (1) the 10 Mbps TP squelch
algorithm is not used for link integrity but to sense the
beginning of a packet, (2) the receiver goes into the
unsquelch state if the input voltage exceeds the squelch
levels for three bit times with alternating polarity within a
50-250 nS interval, (3) the receiver goes into the squelch
state when dle s detected, (4) unsquelch detection has no
affect on link integrity, link pulses are used for that in 10
Mbps mode, (5) start of packet is determined when the
receiver goes into the unsquelch state and CRS is as-
serted, and (6) the receiver meets the squelch require-
ments defined in IEEE 802.3 Clause 14.
3.9.5 Equalizer Disable
The adaptive equalizer can be disabled by setting the
equalizer disable bit in the MI serial port Configuration 1
register. When disabled, the equalizer is forced into the
response it would normally have if zero cable length was
detected.
3.9.6 Receive Level Adjust
The receiver squelch and unsquelch evels can be owered
by 4.5 dB by setting the receive level adjust bit in the MI
serial port Configuration 1 register. By setting this bit, the
device may be able to support longer cable lengths.
Figure 5. TP Input Voltage Template-10Mbps
3.1 V
a. Short Bit
585 mV
585 mV sin ( t/PW)
PW
0
Slope 0.5 V/ns
3.1 V
b. Long Bit
585 mV
585 mV sin [2 (t – PW/2)/PW]
PW/4
0
PW
3PW/4
Slope 0.5 V/ns
585 mV sin (2 t/PW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LQT100X | Peripheral IC |
| LQT1KX | Peripheral IC |
| LQT50X3 | Peripheral IC |
| LQT60X3 | Peripheral IC |
| LQV3M2768-3CGR | Peripheral IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LQ821 | 制造商:POLYFET 制造商全稱:Polyfet RF Devices 功能描述:SILICON GATE ENHANCEMENT MODE RF POWER LDMOS TRANSISTOR |
| LQ9D161 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:DEVICE SPECIFICATION FOR TFT-LCD module |
| LQ9D340 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:Color TFT-LCD Module for Measuring instruments/Banking terminals |
| LQA03TC600 | 功能描述:整流器 Q-Series 600V 3A Ultra Low Qrr RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時(shí)間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
| LQA05TC600 | 功能描述:整流器 Q-Series 600V 5A Ultra Low Qrr RoHS:否 制造商:Vishay Semiconductors 產(chǎn)品:Standard Recovery Rectifiers 配置: 反向電壓:100 V 正向電壓下降: 恢復(fù)時(shí)間:1.2 us 正向連續(xù)電流:2 A 最大浪涌電流:35 A 反向電流 IR:5 uA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DO-221AC 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。