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參數(shù)資料
| 型號： | LQ80221 |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 27/91頁 |
| 文件大?。?/td> | 907K |
| 代理商： | LQ80221 |
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80220/80221
4-27
MD400159/E
Table 5. LED Normal Function Definition
BITS
17.7-6
PLED5
PLED4
PLED3
PLED2
PLED1
PLED0
11
RCV
ACT
XMT
ACT
LINK
COL
FDX
10/100
10
RCV
ACT
XMT
ACT
LINK
ACT
FDX
10/100
01
RCV
ACT
XMT
ACT
LINK
+ ACT
COL
FDX
10/100
00
RCV
ACT
XMT
ACT
LINK
100
ACT
FDX
LINK10
Device powers up with default set to 00.
Table 6. LED Event Definition
Symbol
Definition
XMT ACT
Transmit Activity Occurred, Stretch Pulse
to 100 mS
RCV ACT
Receive Activity Occurred, Stretch Pulse
to 100 mS
ACT
Activity Occurred, Stretch Pulse
to 100 mS
COL
Collision Occurred, Stretch Pulse
to 100 mS
LINK100
100 Mb Link Detected
LINK10
10 Mb Link Detected
LINK
100 or 10 Mb Link Detected
LINK+ACT
100 or 10 Mb Link Detected or Activity
Occurred, Stretch Pulse To 100 mS
(Link Detect Causes LED to be On,
Activity Causes LED to Blink)
FDX
Full Duplex Mode Enabled
10/100
10 Mb Mode Enabled (High), or 100 Mb
Mode Enabled (Low)
3.24 100BASE-T4 INTERFACE
The 80220/80221 has a 100Base-T4 (referred to as T4)
interface to an external 100Base-T4 transceiver. This
interface is available only on the 80221 64L version. The
T4 interface is intended to allow the 80220/80221 to be
able to perform AutoNegotiation with T4 as one of the
advertised capabilities, then enable an external T4 trans-
ceiver if T4 is chosen as the operating mode at the
conclusion of the AutoNegotiation process, and then turn
over control of the TP cable to the external T4 transceiver.
The 80220/80221 will advertise T4 as one of its capabili-
ties if either the T4ADV pin is asserted or the T4 capability
bit is set in the MI serial port AutoNegotiation Advertise-
ment register. If the AutoNegotiation process is initiated
with the T4ADV pin asserted, T4 will be advertised along
with any other capabilities written into the MI serial port
AutoNegotiation Advertisement register. The
AutoNegotiation process will then proceed as outlined in
the Link Integrity & AutoNegotiation section with the addi-
tion of factoring T4 into the AutoNegotiation algorithm
along with the other advertised capabilities. If T4 is
selected by the AutoNegotiation process as the mode to
be enabled, then the T4OE pin is asserted to enable an
external T4 transceiver and the 80220/80221 transmitter
is placed in the high impedance mode. The 80220/80221
then waits o see f he external T4 ransceiver goes nto he
Link Pass state. If he external T4 ransceiver goes nto ink
pass within the required time, it has to assert the T4LNK
input to the 80220/80221. In response, the 80220/80221
keeps the T4OE pin asserted and TP transmitter stays in
high impedance. If the T4LNK pin doesn't get asserted
within the required time, then the AutoNegotiation process
restarts with the T4OE pin deasserted and 80220/80221
transmitter activated. If the T4OE output is asserted and
the T4LNK input goes from asserted to deasserted, the
AutoNegotiation process restarts with the T4OE pin
deasserted and 80220/80221 transmitter activated.
3.25 REPEATER MODE
The 80221 has one predefined repeater mode which can
be enabled by asserting he RPTR pin. When his repeater
mode is enabled with the RPTR pin, the device operation
is altered as follows: (1) TX_EN to CRS loopback is
disabled, (2) AutoNegotiation is disabled, (3) 100 Mbps
operation is enabled, and (4) Half Duplex operation is
enabled. The RPTR pin is only available on the 80221
(64L version), and not available on the 80220 (44L ver-
sion). Note that the repeater mode enabled by the RPTR
pin s only one of many possible repeater modes available
on the device; other repeater modes are available on both
the 80220 and 80221 by setting the appropriate register
bits to enable or disable the desired functions for a given
repeater mode type. See the Repeater Applications
Section (5.10.2) for more details on other possible re-
peater modes.
3.26 MI SERIAL PORT
3.26.1 Signal Description
The MI serial port has eight pins, MDC, MDIO, MDINT,
and MDA[4:0]. MDC is the serial shift clock input. MDIO
is a bidirectional data I/O pin. MDINT s an nterrupt output.
MDA[4:0] are address pins for the MI serial port.
MDA[4:0] inputs share the same pins as the MDINT and
PLED[3:0] outputs, respectively. At powerup or reset, the
PLED[3:0] and MDINT output drivers are tristated for an
interval called the power-on reset time. During the power-
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