參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 51/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
51 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
When bit PWRON is logic 0, the RD_N, WR_N and CS_N signals are floating
because the microprocessor is not powered. To protect the ISP1582 registers from
being corrupted during suspend, register write is locked when the chip goes into
suspend. Therefore, you need to issue the Unlock command to unlock the ISP1582
registers.
9.5.6
Test Mode register (address: 84h)
This 1-byte register allows the firmware to set pins DP and DM to predetermined
states for testing purposes. The bit allocation is given in
Table 75
.
Remark:
Only one bit can be set to logic 1 at a time. This must be implemented for
the Hi-Speed USB logo compliance testing.
[1]
[2]
Either FORCEHS or FORCEFS should be set at a time.
Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit should be set at a time.
Table 75:
Bit
Symbol
Reset
Bus reset
Access
Test Mode register: bit allocation
7
FORCEHS
0
0
R/W
6
5
4
3
2
1
0
reserved
FORCEFS
0
0
R/W
PRBS
0
0
R/W
KSTATE
0
0
R/W
JSTATE
0
0
R/W
SE0_NAK
0
0
R/W
-
-
-
-
R/W
R/W
Table 76:
Bit
7
Test Mode register: bit description
Symbol
Description
FORCEHS
logic 1
[1]
forces the hardware to high-speed mode only and
disables the chirp detection logic.
-
reserved.
FORCEFS
logic 1
[1]
forces the physical layer to full-speed mode only and
disables the chirp detection logic.
PRBS
logic 1
[2]
sets pins DP and DM to toggle in a predetermined
random pattern.
KSTATE
writing logic 1
[2]
sets pins DP and DM to the K state.
JSTATE
writing logic 1
[2]
sets pins DP and DM to the J state.
SE0_NAK
writing logic 1
[2]
sets pins DP and DM to a high-speed quiescent
state. The device only responds to a valid high-speed IN token
with a NAK.
6 to 5
4
3
2
1
0
相關(guān)PDF資料
PDF描述
ISP1583 Hi-Speed Universal Serial Bus peripheral controller
ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
ISP1760BE Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications
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