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參數(shù)資料
| 型號： | ISP1582BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC56 |
| 封裝： | 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56 |
| 文件頁數(shù)： | 28/66頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ISP1582BS |
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Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
28 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
First NAK: the first NAK on an IN or OUT token after a previous ACK response.
9.2.4
OTG register (address: 12h)
The bit allocation of the OTG register is given in
Table 26
.
Table 25:
Value
00h
Debug mode settings
CDBGMOD
interrupt on all ACK and
NAK
interrupt on all ACK.
interrupt on all ACK and
first NAK
[1]
DDBGMODIN
interrupt on all ACK and
NAK
interrupt on ACK
interrupt on all ACK and
first NAK
[1]
DDBGMODOUT
interrupt on all ACK, NYET
and NAK
interrupt on ACK and NYET
interrupt on all ACK, NYET
and first NAK
[1]
01h
1Xh
Table 26:
Bit
Symbol
Reset
Bus reset
Access
OTG register: bit allocation
7
reserved
-
-
-
6
5
4
3
2
1
0
DP
0
0
R/W
BSESSVALID
-
-
R/W
INITCOND
-
-
R/W
DISCV
0
0
R/W
VP
0
0
R/W
OTG
0
0
R/W
-
-
-
Table 27:
Bit
7 to 6 -
5
OTG register: bit description
[1][2][3]
Symbol
Description
reserved
DP
When set, data-line pulsing is started. The default value of this bit is
logic 0. This bit must be cleared when data-line pulsing is completed.
BSESS VALID The device can initiate another V
BUS
discharge sequence after
data-line pulsing and V
BUS
pulsing, and before it clears this bit and
detects a session valid.
This bit is latched to logic 1 once V
BUS
exceeds the B-device session
valid threshold. Once set, it remains at logic 1. To clear this bit, write
logic 1. (The ISP1582 continuously updates this bit to logic 1 when
the B-session is valid. If the B-session is valid after it is cleared, it is
set back to logic 1 by the ISP1582).
4
0 —
It implies that SRP has failed. To proceed to a normal operation,
the device can restart SRP, clear bit OTG or proceed to an error
handling process.
1 —
It implies that the B-session is valid. The device clears bit OTG,
goes into normal operation mode, and sets bit SOFTCT (DP pull-up)
in the Mode register. The OTG host has a maximum of 5 s before it
responds to a session request. During this period, the ISP1582 may
request to suspend. Therefore, the device firmware must wait for
sometime if it wishes to know the SRP result (success—if there is
minimum response from the host within 5 s; failure—if there is no
response from the host within 5 s).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1582BS,518 | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,551 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,557 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BSGA | 功能描述:IC UBS CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1582BS-S | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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