參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 40/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
40 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.4.2
DMA Transfer Counter register (address: 34h)
This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It
indicates the remaining number of bytes left for transfer. The bit allocation is given in
Table 50
.
For IN endpoint —
As there is a FIFO in the ISP1582 DMA controller, some data
may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes,
and the maximum delay time for the data to be shifted to endpoint buffer is 60 ns.
For OUT endpoint —
Data will not be cleared for the endpoint buffer until all the data
has been read from the DMA FIFO.
If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover
when it reaches zero.
Table 48:
Bit
7 to 0
DMA Command register: bit description
Symbol
Description
DMA_CMD[7:0]
DMA command code; see
Table 49
.
Table 49:
Code
00h
DMA commands
Name
GDMA Read
Description
Generic DMA IN token transfer (slave mode only):
Data is transferred from the external
DMA bus to the internal buffer. Strobe: DIOW by external DMA controller.
Generic DMA OUT token transfer (slave mode only):
Data is transferred from the internal
buffer to the external DMA bus. Strobe: DIOR by external DMA controller.
reserved
Validate Buffer (for debugging only):
Request from the microcontroller to validate the
endpoint buffer following a DMA to USB data transfer.
Clear Buffer:
Request from the microcontroller to clear the endpoint buffer after a USB to
DMA data transfer.
reserved
Reset DMA:
Initializes the DMA core to its power-on reset state.
Remark:
When the DMA core is reset during the Reset DMA command, the DREQ, DACK,
DIOW and DIOR handshake pins will be temporarily asserted. This can confuse the external
DMA controller. To prevent this, start the external DMA controller
only after
the DMA reset.
reserved
GDMA stop
: This command stops the GDMA data transfer. Any data in the OUT endpoint
that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint
will be written to the endpoint buffer. An interrupt bit will be set to indicate the completion of
the DMA Stop command.
reserved
01h
GDMA Write
02h to 0Dh
0Eh
-
Validate Buffer
0Fh
Clear Buffer
10h
11h
-
Reset DMA
12h
13h
-
GDMA Stop
14h to FFh
-
Table 50:
Bit
Symbol
Reset
Bus reset
Access
DMA Transfer Counter register: bit allocation
31
30
29
28
27
26
25
24
DMACR4 = DMACR[31:24]
0
0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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