參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁(yè)數(shù): 13/66頁(yè)
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
13 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
[2]
[3]
[4]
X: Don’t care.
Dead: The USB cable is plugged-out and V
CC(I/O)
is not available.
Plug-out: The USB cable is not present but V
CC(I/O)
is available.
Plug-in: The USB cable is being plugged-in and V
CC(I/O)
is available.
8.11 Interrupt
8.11.1
Interrupt output pin
The Interrupt Configuration register of the ISP1582 controls the behavior of the INT
output pin. The polarity and signaling mode of pin INT can be programmed by setting
bits INTPOL and INTLVL of the Interrupt Configuration register (R/W: 10h); see
Table 24
. Bit GLINTENA of the Mode register (R/W: OCh) is used to enable pin INT.
Default settings after reset are active LOW and level mode. When pulse mode is
selected, a pulse of 60 ns is generated when the OR-ed combination of all interrupt
bits changes from logic 0 to logic 1.
Figure 4
shows the relationship between the interrupt events and pin INT.
Each of the indicated USB and DMA events is logged in a status bit of the Interrupt
register and the DMA Interrupt Reason register, respectively. Corresponding bits in
the Interrupt Enable register and the DMA Interrupt Enable register determine
whether or not an event will generate an interrupt.
Interrupts can be masked globally by means of bit GLINTENA of the Mode register;
see
Table 21
.
Field CDBGMOD[1:0] of the Interrupt Configuration register controls the generation
of the INT signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt
Configuration register controls the generation of the INT signals for the IN pipe. Field
DDBGMODOUT[1:0] of the Interrupt Configuration register controls the generation of
the INT signals for the OUT pipe; see
Table 25
.
Table 3:
V
CC
ISP1582 pin status
[1]
V
CC(I/O)
State
Pin
RESET_N
X
X
X
LOW
HIGH
INT_N
X
LOW
LOW
HIGH
HIGH
SUSPEND
X
HIGH
HIGH
LOW
LOW
DREQ
X
high-Z
high-Z
high-Z
high-Z
DATA[15:0]
X
input
high-Z
high-Z
high-Z
0 V
0 V
0 V
>
3.3 V
3.3 V
3.3 V
V
CC
V
CC
V
CC
V
CC
V
CC
dead
[2]
plug-out
[3]
plug-in
[4]
reset
normal
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