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參數(shù)資料
| 型號(hào)： | ISP1582BS |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQCC56 |
| 封裝： | 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56 |
| 文件頁數(shù)： | 27/66頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ISP1582BS |
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Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
27 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
If OTG is logic 0, the status of the pull-up resistor on DP is referred to in
Table 22
.
9.2.3
Interrupt Configuration register (address: 10h)
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
Table 23
. When the USB SIE receives or generates an ACK,
NAK or STALL, it will generate interrupts depending on three Debug mode fields.
CDBGMOD[1:0] —
Interrupts for the control endpoint 0
DDBGMODIN[1:0] —
Interrupts for the DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] —
Interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
you to individually configure when the ISP1582 sends an interrupt to the external
microprocessor.
Table 25
lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising
or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting
INTLVL to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
Table 22:
V
BUS
On
Status of the chip
SoftConnect = on
pull-up resistor on DP
SoftConnect = off
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
Off
pull-up resistor on DP is removed;
suspend interrupt is immediately set,
regardless of the D+ and D
signals
Table 23:
Bit
Symbol
Reset
Bus reset
Access
Interrupt Configuration register: bit allocation
7
6
CDBGMOD[1:0]
1
1
1
1
R/W
R/W
5
4
3
2
1
0
DDBGMODIN[1:0]
1
1
R/W
DDBGMODOUT[1:0]
1
1
R/W
INTLVL
0
unchanged
R/W
INTPOL
0
unchanged
R/W
1
1
1
1
R/W
R/W
Table 24:
Bit
7 to 6
5 to 4
3 to 2
1
Interrupt Configuration register: bit description
Symbol
Description
CDBGMOD[1:0]
Control 0 Debug Mode:
For values, see
Table 25
DDBGMODIN[1:0]
Data Debug Mode IN:
For values, see
Table 25
DDBGMODOUT[1:0]
Data Debug Mode OUT:
For values, see
Table 25
INTLVL
Interrupt Level
: Selects signaling mode on output INT
(0 = level; 1 = pulsed). In pulsed mode, an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
INTPOL
Interrupt Polarity:
Selects signal polarity on output INT
(0 = active LOW; 1 = active HIGH). Bus reset
value: unchanged.
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1582BS,518 | 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,551 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BS,557 | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1582BSGA | 功能描述:IC UBS CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1582BS-S | 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
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