參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 36/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
36 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.3.6
Endpoint MaxPacketSize register (address: 04h)
This register determines the maximum packet size for all endpoints except control 0.
The register contains 2 bytes, and the bit allocation is given in
Table 41
.
Each time the register is written, the Buffer Length registers of all endpoints are
reinitialized to the FFOSZ field value. Bits NTRANS control the number of
transactions allowed in a single microframe (for high-speed isochronous and interrupt
endpoints only).
Table 39:
Bit
Symbol
Reset
Bus reset
Access
Buffer Status register: bit allocation
7
6
5
4
3
2
1
0
reserved
BUF1
0
0
R
BUF0
0
0
R
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Table 40:
Bit
7 to 2
1 to 0
Buffer Status register: bit description
Symbol
Description
-
reserved
BUF[1:0]
00 —
The buffers are not filled.
01 —
One of the buffers is filled.
10 —
One of the buffers is filled.
11 —
Both the buffers are filled.
Table 41:
Bit
Symbol
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
Endpoint MaxPacketSize register: bit allocation
15
14
reserved
-
-
-
-
R/W
R/W
7
6
13
12
11
10
9
8
NTRANS[1:0]
0
0
R/W
4
FFOSZ[7:0]
0
0
R/W
FFOSZ[10:8]
0
0
R/W
1
-
-
0
0
0
0
0
0
R/W
5
R/W
3
R/W
2
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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