參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 44/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
44 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 59
shows the status of the bits in the DMA Interrupt Reason register when the
corresponding bits in the Interrupt register is set.
Table 56:
Bit
Symbol
DMA Interrupt Reason register: bit allocation
15
14
TEST3
13
12
11
10
9
8
reserved
GDMA_
STOP
0
0
R/W
4
EXT_EOT
INT_EOT
reserved
DMA_
XFER_OK
0
0
R/W
0
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
-
-
-
-
-
-
0
0
0
0
-
-
R
7
R
6
R
5
R/W
3
R/W
2
R/W
1
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 57:
Bit
15
DMA Interrupt Reason register: bit description
Symbol
Description
TEST3
This bit is set when the DMA transfer for a packet (OUT transfer)
terminates before the whole packet has been transferred. This
bit is a status bit, and the corresponding mask bit of this register
is always logic 0. Writing any value other than logic 0 has no
effect.
14 to 13 -
reserved
12
GDMA_STOP
When the GDMA_STOP command is issued to the DMA
Command registers, it means the DMA transfer has
successfully terminated.
11
EXT_EOT
Logic 1 indicates that an external EOT is detected. This is
applicable only in GDMA (slave) mode.
10
INT_EOT
Logic 1 indicates that an internal EOT is detected; see
Table 58
.
9
-
reserved
8
DMA_XFER_OK
Logic 1 indicates that the DMA transfer has been completed
(DMA Transfer Counter has become zero). This bit is only used
in GDMA (slave) mode.
7 to 0
-
reserved
Table 58:
INT_EOT
1
Internal EOT-functional relation with bit DMA_XFER_OK
DMA_XFER_OK Description
0
During the DMA transfer, there is a premature termination
with short packet.
1
DMA transfer is completed with short packet and the DMA
transfer counter has reached 0.
1
DMA transfer is completed without any short packet and the
DMA transfer counter has reached 0.
1
0
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