參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 42/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
42 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
The DREQ pin will only be driven only after you perform a write access to the DMA Configuration
register (that is, after you have configured the DMA Configuration register).
9.4.4
DMA Hardware register (address: 3Ch)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table 54
.
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR and DIOW) and DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]) for GDMA
(slave) mode.
Table 53:
Bit
15 to 8
7
DMA Configuration register: bit description
[1]
Symbol
Description
-
reserved
DIS_XFER_CNT Logic 1 disables the DMA Transfer Counter (see
Table 50
). The
transfer counter can be disabled only in GDMA (slave) mode.
-
reserved
MODE[1:0]
These bits only affect the GDMA slave handshake signals.
6 to 4
3 to 2
00 —
DIOW slave strobes data from the DMA bus into the
ISP1582; DIOR slave puts data from the ISP1582 on the DMA
bus
01 —
DACK slave strobes data from the DMA bus into the
ISP1582; DIOR slave puts data from the ISP1582 on the DMA
bus
10 —
DACK slave strobes data from the DMA bus into the
ISP1582 and also puts data from the ISP1582 on the DMA bus.
(This mode is applicable only to the 16-bit DMA; this mode
cannot be used for the 8-bit DMA.)
11 —
reserved.
reserved
This bit selects the DMA bus width for the GDMA slave.
1
0
-
WIDTH
0 —
8-bit data bus
1 —
16-bit data bus.
Table 54:
Bit
Symbol
DMA Hardware register: bit allocation
7
ENDIAN[1:0]
6
5
4
3
2
1
0
EOT_POL
reserved
ACK_POL
DREQ_
POL
1
1
R/W
WRITE_
POL
0
0
R/W
READ_
POL
0
0
R/W
Reset
Bus reset
Access
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
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