參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 45/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
45 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
[1]
1 indicates that the bit is set and 0 indicates that the bit is not set. A bit is set when the corresponding
EOT condition is met. For example; EXT_EOT is set if external EOT conditions are met (pin EOT
active), regardless of other EOT conditions. If multiple EOT conditions are met, the corresponding
interrupt bits are set.
If both EXT_EOT and DMA_XFER_OK conditions are met in DMA for an IN endpoint, the EXT_EOT
interrupt is not set.
The value of INT_EOT may not be accurate if an external or internal transfer counter is programmed
with a value that is lower than the transfer that the host requests. To terminate an OUT transfer with
INT_EOT, the external or internal DMA counter should be programmed as a multiple of the full-packet
length of the DMA endpoint. When a short packet is successfully transferred by DMA, INT_EOT is set.
[2]
[3]
9.4.6
DMA Interrupt Enable register (address: 54h)
This 2-byte register controls the interrupt generation of the source bits in the DMA
Interrupt Reason register. The bit allocation is given in
Table 60
. The bit description is
given in
Table 57
.
Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is
disabled, with the values turning to logic 0.
9.4.7
DMA Endpoint register (address: 58h)
This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA
transfers. The bit allocation is given in
Table 61
.
Table 59:
Status
Status of the bits in the DMA Interrupt Reason register
[1][2]
EXT_EOT
INT_EOT
DMA_XFER_OK
Counter enabled Counter disabled
1
1
1
1
IN full
IN short
OUT full
OUT short
1
1
1
1
0
0
0
0
0
0
0
1
[3]
Table 60:
Bit
Symbol
DMA Interrupt Enable register: bit allocation
15
14
TEST4
13
12
11
10
9
8
reserved
IE_GDMA_
STOP
0
0
R/W
4
IE_EXT_
EOT
0
0
R/W
3
IE_INT_
EOT
0
0
R/W
2
reserved
IE_DMA_
XFER_OK
0
0
R/W
0
Reset
Bus reset
Access
Bit
Symbol
Reset
Bus reset
Access
-
-
-
-
-
6
-
-
-
5
0
0
R
7
R/W
1
reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 61:
Bit
Symbol
Reset
Bus reset
Access
DMA Endpoint register: bit allocation
7
6
5
4
3
2
1
0
reserved
EPIDX[2:0]
0
0
R/W
DMADIR
0
0
R/W
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
R/W
R/W
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