參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 26/66頁
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
26 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
When SoftConnect and V
BUS
are not present (except in OTG), the USB bus activities
are not qualified. Therefore, the chip will follow the suspend command to enter
suspend mode (the clock is controlled by bit CLKAON).
When V
BUS
is off, the 1.5 k
pull-up resister is disconnected from pin DP in
approximately 4 ns via bit SOFTCT in the Mode register and a suspend interrupt is
set with some latency (debounce and disqualify USB traffic).
When bit SOFTCT is set to logic 0, no interrupt is generated. The firmware can issue
a suspend command, followed by the resetting of bit SOFTCT to suspend the chip.
If OTG is logic 1, the pull-up resistor on pin DP depends on D+ line (V
BUS
sensing
status). Bit DP operates as normal, so the firmware must mask suspend and wake-up
interrupt events. When SRP is completed, the device should clear OTG.
7
CLKAON
Clock Always On:
Logic 1 indicates that the internal clocks are
always running when in the suspend state. Logic 0 switches off the
internal oscillator and PLL when the device goes into suspend
mode. The device will consume less power if this bit is set to logic 0.
The clock is stopped after a delay of approximately 2 ms, following
which bit GOSUSP is set.
Send Resume:
Writing logic 1, followed by logic 0 will generate an
upstream resume signal of 10 ms duration, after a 5 ms delay.
Go Suspend:
Writing logic 1, followed by logic 0 will activate
suspend mode.
Soft Reset:
Writing logic 1, followed by logic 0 will enable a
software-initiated reset to the ISP1582. A soft reset is similar to a
hardware-initiated reset (via pin RESET_N).
Global Interrupt Enable:
Logic 1 enables all interrupts. Individual
interrupts can be masked by clearing the corresponding bits in the
Interrupt Enable register.
When this bit is not set, an unmasked interrupt will not generate an
interrupt trigger on the interrupt pin. If global interrupt, however, is
enabled while there is any pending unmasked interrupt, an interrupt
signal will be immediately generated on the interrupt pin. (If the
interrupt is set to pulse mode, the interrupt events that were
generated before the global interrupt is enabled may be dropped).
Wake up on Chip Select:
Logic 1 enables wake-up from suspend
mode through a valid register read on the ISP1582. (A read will
invoke the chip clock to restart. If you write to the register before the
clock gets stable, it may cause malfunctioning).
Pin SUSPEND output control.
6
SNDRSU
5
GOSUSP
4
SFRESET
3
GLINTENA
2
WKUPCS
1
PWRON
0 —
Pin SUSPEND is HIGH when the ISP1582 is in the suspend
state. Otherwise, pin SUSPEND is LOW.
1 —
When the device is woken up from the suspend state, there will
be a 1 ms active HIGH pulse on pin SUSPEND. Pin SUSPEND will
remain LOW in all other states.
SoftConnect:
Logic 1 enables the connection of the 1.5 k
pull-up
resistor on pin RPU to the DP line. Bus reset value: unchanged.
0
SOFTCT
Table 21:
Bit
Mode register: bit description
…continued
Symbol
Description
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