參數(shù)資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁數(shù)： 6/73頁
文件大小： 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
6 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
MODE0/DA1
20
I/O
during power-up
: input to select the read/write strobe
functionality in generic processor mode
0 —
Motorola style: pin 26 is R/W and pin 27 is DS
1 —
8051 style: pin 26 is RD and pin 27 is WR
normal operation
: address output to select the task file
register of an ATAPI device
address output to select the task file register of an ATAPI
device
Generic processor mode
: ready signal (READY; output)
A LOW level signals that ISP1581 is processing a previous
command or data and is not ready for the next command or
data transfer; a HIGH level signals that ISP1581 is ready
for the next microprocessor read or write.
Split Bus mode
: DMA ready signal (IORDY; input); used
for accessing ATAPI peripherals (PIO and UDMA modes
only).
analog ground
supply voltage (3.3 V
±
10%); supplies internal digital
circuits
chip select input
input; function is determined by input MODE0 at power-up:
MODE0 = 0 —
pin functions as R/W (Motorola style)
MODE0 = 1 —
pin functions as RD (8051 style).
input; function is determined by input MODE0 at power-up:
MODE0 = 0 —
pin functions as DS (Motorola style)
MODE0 = 1 —
pin functions as WR (8051 style).
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
input; function determined by input MODE1 during
power-up:
MODE1 = 0 —
address latch enable; a falling edge latches
the address on the multiplexed address/data bus (AD[7:0])
MODE1 = 1 —
address/data selection on AD[7:0]; a logic 1
indicates that an address will be written at the next WR
pulse; a logic 0 indicates that data will be written at the next
WR pulse; used in Split Bus mode only.
bit 0 of multiplexed address/data
bit 1 of multiplexed address/data
bit 2 of multiplexed address/data
bit 3 of multiplexed address/data
bit 4 of multiplexed address/data
bit 5 of multiplexed address/data
digital ground
supply voltage (3.3 or 5.0 V)
bit 6 of multiplexed address/data
DA2
21
O
READY/
IORDY
22
I/O
AGND
V
CC(3.3)
23
24
-
-
CS
(R/W)/RD
25
26
I
I
DS/WR
27
I
INT
28
O
ALE/A0
29
I
AD0
AD1
AD2
AD3
AD4
AD5
DGND
V
CC(5.0)
AD6
30
31
32
33
34
35
36
37
38
I/O
I/O
I/O
I/O
I/O
I/O
-
-
I/O
Table 2:
Symbol
[1]
Pin description for LQFP64
…continued
Pin
Type
[2]
Description
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ISP1582 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed Universal Serial Bus peripheral controller
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