參數(shù)資料
型號(hào): ISP1581
廠商: NXP Semiconductors N.V.
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: 通用串行總線2.0高速接口設(shè)備
文件頁(yè)數(shù): 25/73頁(yè)
文件大?。?/td> 1819K
代理商: ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
25 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
MDMA (Master) read/write (opcode = 06H/07H)
DMA Configuration register (see
Table 35
)
UDMA_MODE[1:0]
determines the MDMA timings for the DIOR and DIOW
strobes (value 03H is used for UDMA only)
determines the active data strobe(s).
selects the DMA bus width: 8 or 16 bits
disables the use of the DMA Transfer Counter
set to logic 1 (ATA transfer)
MODE[1:0]
WIDTH
DIS_XFER_CNT
ATA_MODE
DMA Hardware register (see
Table 37
)
EOT_POL
ACK_POL, DREQ_POL,
WRITE_POL, READ_POL
MASTER
input EOT is not used
select the polarity of the DMA handshake signals
set to logic 1 (master)
Table 29: Control bits for IDE-specified DMA transfers
Control bits
PIO read/write (opcode = 04H/05H)
DMA Configuration register (see
Table 35
)
PIO_MODE[2:0]
ATA_MODE
DMA Hardware register (see
Table 37
)
MASTER
MDMA read/write (opcode = 06H/07H)
DMA Configuration register (see
Table 35
)
MDMA_MODE[1:0]
ATA_MODE
DMA Hardware register (see
Table 37
)
MASTER
UDMA Read/Write (opcode = 02H/03H)
DMA Configuration register (see
Table 35
)
UDMA_MODE[1:0]
IGNORE_IORDY
ATA_MODE
DMA Hardware register (see
Table 37
)
MASTER
Description
selects the PIO mode; timings are ATA(PI) compatible
set to logic 1 (ATA transfer)
set to logic 0
selects the MDMA mode; timings are ATA(PI) compatible
set to logic 1 (ATA transfer)
set to logic 0
selects the UDMA mode; timings are ATA(PI) compatible
used to ignore the IORDY pin during transfer
set to logic 1 (ATA transfer)
set to logic 0
Table 28: Control bits for Generic DMA transfers
…continued
Control bits
Description
相關(guān)PDF資料
PDF描述
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
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