參數(shù)資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁數(shù)： 5/73頁
文件大?。?/td> 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
5 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
6.2 Pin description
Table 2:
Symbol
[1]
DGND
V
CC(5.0)
AGND
V
reg(3.3)
Pin description for LQFP64
Pin
Type
[2]
1
-
2
-
3
-
5
-
Description
digital ground
supply voltage (3.3 or 5.0 V)
analog ground
regulated supply voltage (3.3 V
±
10%) from internal
regulator; supplies internal analog circuits; used to connect
decoupling capacitor and 1.5 k
pull-up resistor on D
+
line
Remark:
Cannot be used to supply external devices.
USB D
connection (analog)
USB D
+
connection (analog)
connection for external pull-up resistor for USB D
+
line;
must be connected to V
reg(3.3)
via a 1.5 k
resistor
connection for external bias resistor; must be connected to
ground via a 12.2 k
(
±
0.1%) resistor
selects function of pin ALE/A0 (in Split Bus mode only):
0 —
ALE function (address latch enable)
1 —
A0 function (address/data indicator).
Remark:
Connect to V
CC(5.0)
in Generic Processor mode.
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset; connect to V
CC
for power-on reset
(internal POR circuit)
End Of Transfer input (programmable polarity, see
Table 37
); used in DMA slave mode only
DMA request (programmable polarity); direction depends
on the bit MASTER in the DMA Hardware register (DMA
master: input, DMA slave: output); see
Table 37
DMA acknowledge (programmable polarity); direction of
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see
Table 37
interrupt request input from ATA/ATAPI peripheral
chip select output for ATAPI device
chip select output for ATAPI device
during power-up
: input to select the bus configuration
0 —
Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate 8/16-bit DMA data bus on DATA[15:0]
1 —
Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit DMA data bus on DATA[15:0].
normal operation
: address output to select the task file
register of an ATAPI device
D
D
+
RPU
5
6
7
AI/O
AI/O
AI
RREF
8
AI
MODE1
9
I
RESET
10
I
EOT
11
I
DREQ
12
I/O
DACK
13
I/O
DIOR
14
I/O
DIOW
15
I/O
INTRQ
CS1
CS0
BUS_CONF/
DA0
16
17
18
19
I
O
O
I/O
相關(guān)PDF資料
PDF描述
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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